XCF01SF48 XILINX [Xilinx, Inc], XCF01SF48 Datasheet - Page 21

• Manufacturer Part Number: XCF01SF48
• Description: Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: XILINX [Xilinx, Inc]

DS123 (v2.6) March 14, 2005
Preliminary Product Specification
TDI
TMS
TCK
TDO
Revision
V
Design
Control
Logic
CCJ
V
CCO
V
CCINT
R
Figure 15: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
XCFxxP
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
Notes:
1 For Mode pin connections and DONE pin pullup value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or
6 For the XCFxxP the CF pin is a bidirectional pin.
V
V
V
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
GND
CCINT
CCO
CCJ
required for high frequency SelectMAP mode configuration. For BUSY pin requirements, refer to
the appropriate FPGA data sheet.
optionally the CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK).
If the XCFxxP PROM's CLKOUT signal is used, then it must be tied to a 4.7K resistor pulled
up to V
External
Oscillator
(2)
(2)
EN_EXT_SEL
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
CCO
OE/RESET
(5)
BUSY
.
CLK
D[0:7]
CF
CEO
TDO
CE
(5)
(6)
(4)
V
CCJ
V
CCO
V
CCINT
XCFxxP
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
V
V
TDI
TMS
TCK
EN_EX_SEL
REV_SEL[1:0]
GND
CCO
CCJ
(2)
(2)
OE/RESET
BUSY
CLK
D[0:7]
CF
CEO
TDO
CE
(5)
(6)
(4)
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
V
CCO
(2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
I/O
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds123_18_100804
I/O
21
(3)