CY14B101L-SP25XI CYPRESS [Cypress Semiconductor], CY14B101L-SP25XI Datasheet - Page 12

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CY14B101L-SP25XI

Manufacturer Part Number
CY14B101L-SP25XI
Description
1 Mbit (128K x 8) nvSRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Switching Waveforms
Notes
Document Number: 001-06400 Rev. *J
t
t
t
t
t
16. The software sequence is clocked on the falling edge of CE controlled READs or OE controlled READs.
17. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
RC
SA
CW
HA
RECALL
Parameter
DQ (DATA)
[17]
ADDRESS
DQ (DATA)
ADDRESS
CE
OE
CE
OE
t
t
t
t
AVAV
AVEL
ELEH
GHAX,
Alt
t
ELAX
t
SA
t
SA
A
A
D
D
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
DATA VALID
D
D
R
R
t
t
Figure 10. CE Controlled Software STORE/RECALL Cycle
t
Figure 11. OE Controlled Software STORE/RECALL Cycle
SCE
RC
E
RC
E
S
S
t
DATA VALID
S
SCE
S
#
#
1
1
t
t
HA
HA
Description
[16, 17]
Min
A
A
25
20
0
1
D
D
D
D
25 ns
t
R
t
R
RC
RC
E
E
S
S
DATA VALID
S
DATA VALID
S
Max
120
#
#
6
6
t
STORE
t
Min
STORE
35
25
0
1
HIGH IMPEDANCE
[17]
[17]
35 ns
HIGH IMPEDANCE
/ t
/ t
RECALL
RECALL
Max
120
Min
45
30
0
1
CY14B101L
45 ns
Page 12 of 18
Max
120
Unit
ns
ns
ns
ns
μs
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