CY14B101L-SZ45XCT Cypress Semiconductor Corp, CY14B101L-SZ45XCT Datasheet
CY14B101L-SZ45XCT
Specifications of CY14B101L-SZ45XCT
Related parts for CY14B101L-SZ45XCT
CY14B101L-SZ45XCT Summary of contents
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... Document Number: 001-06400 Rev Mbit (128K x 8) nvSRAM Functional Description The Cypress CY14B101L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable QuantumTrap cell ...
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... SRAM Write Cycle....................................................... 11 AutoStore or Power Up RECALL .................................... 12 Software Controlled STORE/RECALL Cycle .................. 13 Switching Waveforms ...................................................... 14 Part Numbering Nomenclature ........................................ 15 Ordering Information ........................................................ 15 These parts are not recommended for new designs. ... 15 Package Diagrams ............................................................ 17 Sales, Solutions, and Legal Information ........................ 20 Worldwide Sales and Design Support......................... 20 Products ...................................................................... 20 CY14B101L Page [+] Feedback ...
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... Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM CAP to nonvolatile elements Connect No Connect. This pin is not connected to the die. Document Number: 001-06400 Rev CAP HSB DQ0 DQ1 5 DQ2 Description CY14B101L HSB Top View (not to scale DQ6 ...
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... SRAM. In addition, it provides unlimited RECALL opera- tions from the nonvolatile cells and up to one million STORE operations. SRAM Read The CY14B101L performs a READ cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A determines the 131,072 data bytes accessed. ...
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... SWITCH to complete. when V is less than V HRECALL CC If the CY14B101L WRITE mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition detected. This protects against inadvertent writes during power up or brown out conditions. Noise Considerations The CY14B101L is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 µ ...
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... Customers that want to use a larger V to make sure there is extra store charge should discuss their V size selection with Cypress to understand any impact on CAP the Vcap voltage level at the end CY14B101L value because CAP value CAP period. RECALL ...
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... The six consecutive address locations are in the order listed HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101L, only the lower 16 lines are used to control software modes state depends on the state of OE. The IO table shown is based on OE Low. ...
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... STORE – 0.2V). All others V < 0.2V or > Max, V < V < Max, V < V < > – pin and Vss, 6V rated. CAP Description CY14B101L Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V -40°C to +85°C 2.7V to 3.6V Min Max Commercial Industrial – 0.2V ...
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... MHz 3.0V CC [6] Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. Figure 4. AC Test Loads 3.0V Output 789Ω CY14B101L Max Unit 32-SOIC 48-SSOP Unit °C/W 33.64 32.9 °C/W 13.6 16.35 For Tri-state Specs R1 577Ω ...
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... WE and HSB must be HIGH during SRAM READ cycles. 8. Device is continuously selected with CE and OE both Low. 9. Measured ±200 mV from steady state output voltage. 10. HSB must remain high during READ and WRITE cycles. Document Number: 001-06400 Rev Description Min Max CY14B101L Unit Min Max Min Max ...
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... Low when CE goes Low, the outputs remain in the high impedance state. 12 must be greater than V during address transitions. IH Document Number: 001-06400 Rev Description Min Max [11, 12 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE SCE PWE t SD DATA VALID HIGH IMPEDANCE CY14B101L Unit Min Max Min Max LZWE [11, 12] t ...
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... If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place. 15. Industrial Grade devices requires 15 ms max. Document Number: 001-06400 Rev. *K Description Rise Time CC Figure 9. AutoStore/Power Up RECALL t STORE t HRECALL SWITCH . SWITCH CY14B101L CY14B101L Unit Min Max 20 ms 12.5 ms 2.65 V μs 150 No STORE occurs STORE occurs only if a SRAM write ...
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... The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles. Document Number: 001-06400 Rev. *K [16, 17 Description Min DATA VALID DATA VALID CY14B101L Max Min Max Min Max 120 120 120 [17 STORE RECALL HIGH IMPEDANCE [17 STORE RECALL ...
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... Commands such as Store and Recall lock out I/O until operation is complete which further increases this time. See specific command. Document Number: 001-06400 Rev. *K Description Figure 12. Hardware STORE Cycle [19, 20] Figure 13. Soft Sequence Processing to allow read and write cycles to complete. DELAY CY14B101L CY14B101L Unit Min Max 15 ns μ ...
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... These parts are not recommended for new designs. Speed Ordering Code (ns) 25 CY14B101L-SZ25XCT CY14B101L-SZ25XC CY14B101LL-SP25XCT CY14B101LL-SP25XC CY14B101L-SZ25XIT CY14B101L-SZ25XI CY14B101L-SP25XIT CY14B101L-SP25XI Document Number: 001-06400 Rev. *K Option T - Tape and Reel Blank - Std. Temperature C - Commercial (0 to 70° Industrial (–40 to 85°C) Package SOIC SSOP ...
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... CY14B101L-SZ35XCT CY14B101L-SZ35XC CY14B101L-SP35XCT CY14B101L-SP35XC CY14B101L-SZ35XIT CY14B101L-SZ35XI CY14B101L-SP35XIT CY14B101L-SP35XI 45 CY14B101L-SZ45XCT CY14B101L-SZ45XC CY14B101L-SP45XCT CY14B101L-SP45XC CY14B101L-SZ45XIT CY14B101L-SZ45XI CY14B101L-SP45XIT CY14B101L-SP45XI All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts Document Number: 001-06400 Rev. *K ...
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... Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] REFERENCE JEDEC MO-119 0.405[10.287] 0.419[10.642] 32 SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14B101L MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 0.006[0.152] 51-85058 *A 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127-*A Page [+] Feedback ...
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... Package Diagrams (continued) Figure 15. 48-Pin Shrunk Small Outline Package (51-85061) Document Number: 001-06400 Rev. *K CY14B101L 51-85061-*C Page [+] Feedback ...
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... Document History Page Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Orig. of Rev. ECN No. Change ** 425138 TUP *A 437321 TUP *B 471966 TUP *C 503272 PCI *D 597002 TUP *E 688776 VKN *F 1349963 UHA/SFV *G 2427986 GVCH *H 2546756 GVCH/AESA Document Number: 001-06400 Rev. *K Submission Description of Change ...
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... Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Orig. of Rev. ECN No. Change *I 2625139 GVCH/PYRS *J 2695908 GVCH/AESA *K 2814390 GVCH Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...