TMC22151AKHC CADEKA [Cadeka Microcircuits LLC.], TMC22151AKHC Datasheet - Page 9

• Manufacturer Part Number: TMC22151AKHC
• Description: Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
REV. 1.0.0 2/4/03
Reg
0D
0D
0D
0D
0D
0D
0D
0E
0E
0E
0E
0F
0F
0F
0F
0F
0F
10
11
12
13
14
14
14
14
15
15
15
15
16
16
16
16
17
18
19
7-6
7-6
5-4
3-2
1-0
6-5
3-2
7-0
7-0
7-0
7-0
7-6
5-4
2-0
6-2
7-6
5-4
3-2
1-0
7-0
7-0
7-0
Bit
5
4
3
2
1
0
7
4
1
0
3
7
1
0
Active when BUFFER pin set LOW
Name
CEST
CESG
YESG
CESTBY
XFEN
FAST
YWBY
XIP
XSF
YMUX
CMUX
CAT
DCES
IPCF
YCCOMP
SYNC
STS
STB
BTV
AV
AV
STS
VINDO
VDIV
VDOV
NFDLY
SPGIP
MSIP
SG0
YG0
UG0
Buffered register set 0
Sync Pulse Generator
7-0
9-8
7-0
10-8
7-0
7-0
7-0
Chroma error signal
transform
Chroma error signal gain
Luma error signal gain
Chroma error signal
bypass
XLUT filter enable
Adaption speed select
Luma weighting bypass
XLUT input select
XLUT special function
Y output select
C output select
reserved, set to zero
Adaption Threshold
D1 C
Comb filter input select
YC or Composite input
select
Sync processor select
Sync to sync 8 lsbs
Sync to burst
Burst to video
Active video line 8 lsbs
reserved, set to zero
Active video line 2 msbs
reserved, set to zero
Sync to sync 3 msbs
reserved, set to zero
Number of lines in vertical
window
Action inside VINDO
Action outside VINDO
reserved, set to zero
new field detect delay
SPG input select
Mixed sync separator input
select
Msync gain, 8 lsbs
Y gain, 8 lsbs
U gain, 8 lsbs
B
C
Function
R
error signal
Reg
1C
1D
1D
1D
2C
2D
1A
1B
1B
1B
1B
1E
1E
1F
2A
2B
2B
2B
2B
20
20
21
22
23
24
24
24
24
24
25
26
26
26
26
26
27
28
29
7-0
7-6
5-3
1-0
7-0
7-3
1-0
7-1
7-0
7-4
3-0
7-0
7-0
7-0
5-4
2-0
7-0
7-6
2-0
7-0
7-0
7-0
7-0
7-6
5-3
1-0
7-0
7-3
Bit
2
2
0
7
6
3
5
4
3
2
Normalized Subcarrier Frequency
Active when BUFFER pin set HIGH
Name
VG0
YG0
UG0
VG0
YOFF0
YOFF0
SG0
SYSPH0
VAXISO
SYSPH0
FSC
FSC
FSC
FSC
DRFSEL
PFLTBY
CLPSEL
VCLPEN
BAND
CPDLY
LDVIO
OPCKS
DPCEN
DPC
SG1
YG1
UG1
VG1
YG1
UG1
VG1
YOFF1
Output Format Control
Buffered register set 1
7-0
9-8
9-8
7-0
3-0
11-4
19-12
27-20
7-0
7-0
7-0
9-8
9-8
10-8
7-0
10-8
Clamp Control
2-0
7-0
8
7-0
14-7
7-0
1-0
6-0
V gain, 8 lsbs
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Y offset, msb
Msync gain, 2 msbs
7 lsbs of phase
V axis flip
8 msbs of phase
Bottom 4 bits of f
reserved, set to zero
Lower 8 bits of f
Middle 8 bits of f
Top 8 bits of f
Clamp pulse enable
Phase filter enable
Int. clamp selection
Clamp bypass
Clamp offset
Clamp pulse delay
reserved, set to zero
LDV clock select
Output clock select
DPC enable
Decoder product code
Msync gain, 8 lsbs
Y gain, 8 lsbs
U gain, 8 lsbs
V gain, 8 lsbs
Y gain, 2 msbs
U gain, 3 msbs
reserved, set to zero
V gain, 2 msbs
Y offset, 8 lsbs
reserved, set to zero
Function
SC
SC
SC
TMC22x5yA
SC
9