TMC22191 CADEKA [Cadeka Microcircuits LLC.], TMC22191 Datasheet
TMC22191
Related parts for TMC22191
TMC22191 Summary of contents
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... SMPTE 170M NTSC or CCIR Report 624 PAL compatible • Supports PAL-M and NTSC without pedestal • Simultaneous S-VIDEO (Y/C) NTSC/PAL output • 10-bit D/A conversion (three channels) Logic Symbol BYPASS and OL 4:0 on TMC22191 only 23 4-0 PDC VHSYNC VVSYNC ...
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... CVBS 7-0 CLOCK CLOCKS Functional Description The TMC22091 and TMC22191 are totally integrated, fully- programmable digital video encoders with simultaneous composite and Y/C (S-VIDEO) outputs. The TMC22x91 video outputs are compatible with SMPTE 170M NTSC, CCIR Report 624 PAL, PAL-M, and NTSC without pedestal television standards ...
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... Figure 1a. Pixel Data Format TMC22091/TMC22191 C 422 format, the interpolation fi 444 for encoding bus, GVSYNC, 7-0 LSB Format Control Register 0 MSB LSB R 00011000 00010000 00011100 R ...
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... C are loaded on alternate LDV cycles B R Figure 1b. Pixel Data Format (TMC22191 when CLUTs are Bypassed) In Slave mode, VHSYNC, VVSYNC, and PDC (optional) are inputs to the TMC22x91. These inputs determine when new lines, frames, and active picture areas begin. The exter- nal controlling circuitry needs to establish the correct timing for these signals ...
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... TMC22090/TMC22190 Compatibility The TMC22090 and TMC22190 are earlier versions of the TMC22091 and TMC22191, respectively. They lack the fol- lowing features of the newer versions: 1. Selectable Setup (to support NTSC EIA-J video output for Japan) 2 ...
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... TMC22091/TMC22191 Pin Assignments 84 Lead PLCC 1 84 100 Lead MQFP 100 1 6 Pin Name Pin Name 1 CVBS 22 TDO 2 2 CVBS 23 TCK 1 3 CVBS 24 TMS 0 4 KEY 25 TDI 5 RESET R/W 28 BYPASS (TEST GND ...
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... PD port when the KEY signal is invoked is at the midpoint of the soft key transition. When HKEN is LOW, KEY is ignored. Like PD data, KEY is clocked into the TMC22x91 on the rising edge of LDV. TMC22091/TMC22191 C , GBR, RGB, and color-indexed B R ...
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... TTL CLUT Bypass Control (TMC22191 only). When BYPASS is HIGH, the CLUT is in the pixel data path within the TMC22191. When BYPASS is LOW, pixel data bypasses the CLUT. BYPASS is active only for certain modes of the Layering Control Register (LCR) when the Format Control Register bit 6 is HIGH ...
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... Scan Select Input. Boundary scan (HIGH)/normal operation (LOW) selector. TTL Scan Clock Input. Boundary scan clock. TTL Data Output Port. Boundary scan data output port Positive digital power supply Positive analog power supply. 0.0 V Digital Ground. 0.0 V Analog Ground. TMC22091/TMC22191 . 7-0 and A . Output video levels GND . REF 9 ...
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... Global Control 2. Format Control 3. Interface Control 4. Test Control 5. Key Control 6. Misc. Control 7. Standards Control 8. Layering Control (TMC22191) 9. Key Value 10. Timing 11. Subcarrier 12. Test I/O 13. Mask Register An external controller loads the Control Registers through a standard interface port. It also loads the CLUT and reads its Value Pin Function Description 0 ...
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... Key Control Register Layering Control Register (TMC22191 input format 04 3-1 input mode 04 0 Key Value Registers 05 7-0 06 7-0 TMC22091/TMC22191 (continued) Name Function FBDIS Frame buffer signals disable ...
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... For each register listed above, all bits not listed are reserved and should be set to zero to ensure proper operation. 3. The meaning of Register 04 (Key Control Register/Layer- ing Control Register) is determined by Format Control Register bit 6 (TMC22191). PRODUCT SPECIFICATION (continued) Name Function FP Front porch length ...
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... RESET is LOW. When HRESET is HIGH, a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken HIGH. SRESET is ignored. The D/A converters remain active during the reset sequence SRESET PAL LUMDIS TMC22091/TMC22191 1 0 CHRDIS HRESET 13 ...
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... Layering Control Register enable. When LOW, the Layering Control Register is not available and Key Control Register functions are enabled. In this mode, the TMC22191 functions like the TMC22091. When HIGH, the Layering Control Register takes the place of the Key Control Register and enables the layering functions. Data loaded into the Key or Layering Control Registers will remain but have a different meaning if this bit is changed ...
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... When HIGH, PDC is an input, and directs the encoder to accept data from the frame buffer FLDLK Field lock select. When LOW, (in Slave mode) the encoder locks to each new field. When HIGH, the encoder locks to field 1 only. (continued TBASE SOUT TMC22091/TMC22191 FBDIS PDCDIR FLDLK 15 ...
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... TMC22091/TMC22191 Control Register Definitions Test Control Register (03 Reserved LIMEN TESTEN Reg Bit Name Function 03 7 Reserved LIMEN Luminance limiter enable. When LOW, all luminance values are passed to modulator. when HIGH, luminance values are limited to 101 IRE TESTEN Test enable ...
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... This function is enabled when Layering Control Register is enabled (TMC22191 EKDIS Blue/green/C enabled for data keying. When HIGH, Blue/green/C data keying. This function is enabled when Layering Control Register is enabled (TMC22191 FKDIS Red/blue/C for data keying. When HIGH, red/blue/C This function is enabled when Layering Control Register is enabled (TMC22191). ...
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... Hardware key enable. When LOW, the KEY input pin ignored. When HIGH, the KEY input pin is enabled BUKEN Burst key enable. When LOW, output video burst is generated on TMC22191. When HIGH, output burst is taken from genlock input data SKEXT Data key operation select. When LOW, data keying is allowed only during active video ...
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... When HIGH, the true value for EH and SL is offset by 512 CB100 NTSC/PAL color bars select. When HIGH, color bars with 100% white level are selected. When LOW, color bars will have 75% white level. (continued FKREN RATIO TFLK TMC22091/TMC22191 1 0 T512 CB100 19 ...
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... TMC22091/TMC22191 Control Register Definitions Standards Control Register (0F EFEN SIX25 PALID Reg Bit Name Function 0F 7 EFEN Same as Register 0E bit 7, but read-only SIX25 Select 625 lines per frame. When HIGH, the encoder assumes 625 line per frame. When LOW, 525 lines per frame are assumed. ...
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... VHSYNC. They allow the user to determine field type on a continuous basis. 1F 4-0 LTYPE Line type identification (read only). These five bits are updates 5 PXCK periods after each VHSYNC. They allow the user to determine line type on a continuous basis. (continued TMC22091/TMC22191 LTYPE ...
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... TMC22091/TMC22191 Control Register Definitions Subcarrier Registers (20-27) Reg Bit Name Function 20 7-0 FREQL Subcarrier frequency 4th byte (LSBs). This 8-bit register holds the LSB (bits 7-0) of the 32-bit subcarrier frequency value (non-genlock modes). The next eight most significant bits are held in Register 21. 21 7-0 FREQ3 Subcarrier frequency 3rd byte ...
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... Y, B-Y, R-Y data to the CLUT, gain and offset fac- tors are needed. Table 4 specifies the recommended transfer functions. The CLUT is loaded in Y-C Overlay Operation For the TMC22091 and TMC22191 (when Format Control Register Bit 6 = LOW), the OL CCIR-601 operation, the nominal data range for Y is from 16 to 235 and for C ...
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... Table 5. CLUT Locations Addressed by Overlay Inputs (TMC22191) OL CLUT location 4 • • • • Table 6. Pixel Input Operation for Format Control Register bit 6 = HIGH (TMC22191) Format Control Register FORMAT Bit 3,2 00 (RGB (GBR Format Control Register Bit 6 = HIGH MSB 15 ...
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... XBP begins after the end of burst, BU, taking the place of CBP in vertical interval UBV lines. Figure 5 shows the verti- cal sync and equalization pulse detail Table 8. Vertical Timing Specifications Parameter NTSC-M PAL 63.5556 64 EH 29.4778 29.65 EL 2.3 2.35 SH 4.7 4.7 SL 27.1 27.3 TMC22091/TMC22191 PAL 1.9 4.95 0.9 2.25 1.8 51.692 63.492 PAL 63.492 29.45 2.3 4.65 27.1 25 ...
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... TMC22091/TMC22191 Burst Figure 3. Horizontal Blanking Interval Timing FIELDS 1 AND 3 524 523 PRE-EQUALIZATION UVV UVV VHSYNC VVSYNC COMPOSITE SYNC 262 263 FIELDS 2 AND 4 264 265 UVV UVE EE EE VHSYNC VVSYNC COMPOSITE SYNC 24318B Figure 4. Sync and Equalization Pulse Detail Timing ...
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... UBB Black burst UVE Half-line video, half-line equalization pulse are used as inputs (Slave mode), their falling edges mark the beginning of the sync interval and the width of the input pulse is specified under Operating Conditions. TMC22091/TMC22191 Field 4 FIELD ID = x11 ID LTYPE Line ID EE ...
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... TMC22091/TMC22191 1247 1248 FIELDS 1 AND 5 1249 1250 UVV VHSYNC VVSYNC COMPOSITE SYNC 309 310 FIELDS 2 AND 6 311 312 UVV VHSYNC VVSYNC COMPOSITE SYNC 622 623 FIELDS 3 AND 7 624 625 UVV VHSYNC VVSYNC COMPOSITE SYNC 934 935 FIELDS 4 AND 8 ...
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... Half-line vertical sync pulse, half-line equalization pulse ES Half-line equalization pulse, half-line vertical sync pulse UBB Black burst UVV Active video UVE Half-line video, half-line equalization pulse UBV half-line black, half-line video TMC22091/TMC22191 Field 4 FIELD ID = 011, 111 LTYPE Line ID LTYPE 03 938 ES 01 ...
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... TMC22091/TMC22191 521 522 523 524 525 UVV UVV EE EE VHSYNC VVSYNC COMPOSITE SYNC 259 260 261 262 UVV VHSYNC VVSYNC COMPOSITE SYNC 521 522 523 524 525 UVV VHSYNC VVSYNC COMPOSITE SYNC 260 258 259 261 262 UVV ...
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... Half-line vertical sync pulse, half-line equalization pulse ES Half-line equalization pulse, half-line vertical sync pulse UBB Black burst UVV Active video UVE Half-line video, half-line equalization pulse UBV half-line black, half-line video TMC22091/TMC22191 Field 4 FIELD ID = 011, 111 LTYPE Line ID LTYPE 03 263 ES 01 ...
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... TMC22091/TMC22191 Table 12. Standard Timing Parameters Field Horizontal Pixel Rate Freq. Rate Standard (Hz) (kHz) (Mpps) NTSC sqr. 59.94 15.734266 12.27 pixel NTSC 59.94 15.734266 13.50 CCIR-601 NTSC 4x 59.94 15.734266 14. PAL sqr. 50.00 15.625000 14.75 pixel PAL 50.00 15.625000 13.50 CCIR-601 PAL 15 50.00 15.625000 15.00 Mpps PAL-M 60.00 15.750000 12.50 sqr.pixel PAL-M 60.00 15,750000 13.50 CCIR-601 PAL ...
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... TMC22091/TMC22191 1135 625 32 -------------------------------------------------- - 2 pixels/line FREQ = --------------- - = BURPH 17 2 909 4 32 ----------------------------- 2 pixels/line FREQ = --------------- - = BURPH 17 2 Subcarrier Register (hex) SYSPHL FREQM FREQ2 FREQ3 ...
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... TMC22091/TMC22191 SCH Phase Error Correction SCH refers to the timing relationship between the 50% point of the leading edge of horizontal sync and the positive or negative zero-crossing of the color burst subcarrier refer- ence. SCH error is usually expressed in degrees of subcarrier phase. In PAL, SCH is defined for line 1 of field 1, but since there is no color burst on line 1, SCH is usually measured at line 7 of fi ...
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... One additional falling edge needed to move input data to the assigned working registers. t PWLCS t PWHCS Figure 10. Microprocessor Port – Write Timing t PWLCS t PWHCS HOM t DOM t DOZ Figure 11. Microprocessor Port – Read Timing TMC22091/TMC22191 during the subsequent rising edge of 7-0 24323A 24324A 35 ...
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... TMC22091/TMC22191 In read mode, the address is accompanied by a HIGH on the R/W pin during a falling edge of CS. The data output pins low-impedance state t ns after CS falls. Valid data is DOZ present after the falling edge of CS. Because 7-0 DOM this port operates asynchronously with the pixel timing, there is an uncertainty in this data valid output delay of one PXCK period ...
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... early, the line will be started early, maintaining the 52 clock delay to out- put comes late, the front porch portion of the output waveform will be extended as necessary. See Figure 15, Slave Mode Timing. TMC22091/TMC22191 2N+3 t PWLLDV 24340A 51 52 ...
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... TMC22091/TMC22191 PXCK VHSYNC 1 VVSYNC 1 for field 1 COMPOSITE OUTPUT PXCK GHSYNC VHSYNC COMPOSITE OUTPUT Genlocked Mode In Genlocked mode, the encoder receives sync signals over the GHSYNC and GVSYNC inputs, and provides VHSYNC and VVSYNC to the host. The 50% sync amplitude point occurs 50 PXCK clocks after GHSYNC goes LOW, while VHSYNC is produced at clock 13 ...
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... The interpo- lated pixels are designated PI in the diagram Figure 18. Internal Pixel Data Control TMC22091/TMC22191 24358A ...
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... The MIDGROUND layer keys over BACKGROUND, but not over FOREGROUND or DOWNSTREAM KEY. 4. The BACKGROUND layer never keys over any other layer important not to confuse layers with sources. The TMC22191 can be programmed to assign any of its input sources (RGB CVBS bus, Overlay bits) to any the four layers ...
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... HI KIDS ! Figure 20. Adding a 3rd Layer In this illustration, all four source images are static (not mov- ing). The images input to the TMC22191 can just as well be "live" (from video camera or VCR sources) as long as: • Data from those sources input format that the TMC22191 can accept, and • ...
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... Example apply to the TMC22091. The result of keying is an effect where a MIDGROUND source image (i.e. Happy Face from PD data) is superimposed over a BACKGROUND source image (i.e. variable matte color from CVBS data). Table 14. Layer Assignments, Image Sources, and Keying Controls (TMC22191) LCR 04 Background LAYMODE Image Source ...
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... COMPOSITE OUTPUT * KEY is advanced five PXCK cycles when Control Register OE bit 4 is HIGH (TMC22191). The key registers may be individually enabled using bits 3,2,1 of the Key Control Register. Bit 4 of the same register enables/disables Data Keying in its entirety. Data Keying and Hardware Keying are logically ORed: when both are enabled, either one will result in a key switch to the CVBS channel ...
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... TMC22091/TMC22191 Genlock Interface The TMC22x91 can process digital composite video connected to its CVBS port. It has been designed to couple tightly with the companion TMC22071 Genlocking Video Digitizer, but it will work with other sources as well. The digital composite video has standard 8-bit binary format at a PXCK/2 rate ...
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... Figure 28. Chroma Modulator and Luminance All digital-to-analog reconstruction systems exhibit a high is the PXCK S frequency roll-off as a result of the zero-order hold charac- teristic of D/A converters. This response is commonly referred sin(x)/x response function of the sam- pling rate of the output D/A. TMC22091/TMC22191 ...
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... TMC22091/TMC22191 The digital interpolation filters in TMC22x91 convert the data stream to a sample rate of twice the pixel rate. As shown in Figures 27 and 28, the filters decrease the sin(x)/x rolloff and the output spectrum between f /4 and 3f S very little energy. Since there is so little signal energy in this frequency band, the demands placed on the output recon- struction fi ...
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... Figure 32. Equivalent Digital Input Circuit t PWLTCK t PWHTCK t HTP t DOTP t HOTP Figure 29. JTAG Test Port Timing 27012A Figure 31. Equivalent Analog Output Circuit 27014A Figure 33. Equivalent Digital Output Circuit TMC22091/TMC22191 24333A COMPOSITE LUMA CHROMA 27013A Output n 27011A 47 ...
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... TMC22091/TMC22191 CS t HOM D 7-0 Figure 34. Transition Levels for Three-State Measurements Absolute Maximum Ratings Parameter Power Supply Voltage Digital Inputs 2 Applied Voltage 3,4 Forced Current Digital Outputs 2 Applied Voltage 3,4 Forced Current Short Circuit Duration (Single output in HIGH state to GND) Analog Output Short Circuit Duration (Single output to GND) ...
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... CS Pulse Width, HIGH PWHCS t Address Setup Time SA t Address Hold Time HA t Data Setup Time (write Data Hold Time (write) HD Min. (2/3)V GND GND = Nom. REF pin) REF = Nom. REF 12.27 24.54 TMC22091/TMC22191 Nom. Max. Units 4.75 5.0 5. 0.8 (1/3)V DD -2.0 4.0 1.235 2.1 3.15 4.4 281 392 588 37 ...
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... TMC22091/TMC22191 Operating Conditions (continued) Parameter t Reset Setup Time SR t Reset Hold Time HR JTAG Interface f Test Clock (TCK) Rate TCK t TCK Pulse Width, LOW PWLTCK t TCK Pulse Width, HIGH PWHTCK t Test Port Setup Time, TDI, TMS STP t Test Port Hold Time, TDI, TMS ...
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... NTSC Conditions PD to Analog Out 4 PXCK to VHSYNC, VVSYNC, PDC 10% to 90% of full-scale 90% to 10% of full-scale Conditions PXCK = 24.54 MHz IRE Ramp PXCK = 24.54 MHz IRE Ramp CCOMP = 0 1kHz TMC22091/TMC22191 Min. Typ. Max. Units PXCK periods 100 ...
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... TMC22091/TMC22191 +5V BYPASS and OL 4-0 on TMC22191 only 4 BYPASS 24 PD 23-0 VHSYNC VVSYNC PDC KEY LDV PXCK 8 CVBS 7-0 GHSYNC GVSYNC 8 2 MICROPROCESSOR INTERFACE Applications Discussion The TMC22x91 is a complex mixed-signal VLSI circuit. It converts digital video signals at clock rates MHz to analog video outputs. A recommended circuit connection is shown in Figure 35 ...
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... CS falling edge. This requirement is usually accomplished by executing the next I/O step. If there is no planned next step in the sequence, executing a Control Register Read step will meet the require- ment and terminate the sequence. TMC22091/TMC22191 TMC22x91 8 27009A must conform to setup ...
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... TMC22091/TMC22191 Table 17. CLUT Read/Write Sequences Step R/W\ A 1-0 Write Entire CLUT Starting at Address ••• ••• ••• 767 0 11 768 0 11 769 0 11 770 1 00 Write CLUT Location address ...
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... F, CLUT address addr. ••• System Modifies d1, e1 d1', e1', f1'. addr Write addr into the CLUT Address Register. (terminates Read sequence) d1’ d1' written into D, CLUT address addr. e1’ e1' written into E, CLUT address addr. f1’ f1' written into F, CLUT address addr. xx Sequence termination. TMC22091/TMC22191 55 ...
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... TMC22091/TMC22191 Notes: 56 PRODUCT SPECIFICATION ...
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... PRODUCT SPECIFICATION Notes: TMC22091/TMC22191 57 ...
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... TMC22091/TMC22191 Mechanical Dimensions – 84-Lead PLCC Package Inches Millimeters Symbol Min. Max. Min. A .165 .200 4.19 A1 .090 .130 2.29 A2 .020 — .51 B .013 .021 .33 B1 .026 .032 .66 D/E 1.185 1.195 30.10 D1/E1 1.150 1.158 29.21 D3/E3 1.000 BSC 25.40 BSC .050 BSC 1.27 BSC e J .042 .056 1.07 ND/ ccc — ...
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... E1 .13 (.005) R Min. E 0.076" (1.95mm) Ref See Lead Detail Base Plane -C- Lead Coplanarity ccc C TMC22091/TMC22191 .20 (.008) Min. 0 Min. .13 (.30) Datum Plane .005 (.012 Lead Detail R 59 ...
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... TMC22091/TMC22191 Ordering Information Product Number Temperature Range TMC22091KHC TMC22091R0C TMC22191KHC TMC22191R0C Screening Package Commercial 100-Lead MQFP Commercial 84-Lead PLCC Commercial 100-Lead MQFP Commercial 84-Lead PLCC PRODUCT SPECIFICATION Package Marking ...