TMC22151AKHC CADEKA [Cadeka Microcircuits LLC.], TMC22151AKHC Datasheet - Page 30

• Manufacturer Part Number: TMC22151AKHC
• Description: Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

TMC22x5yA
Control Register Definitions
Output Format Control (26)
Buffered register set 1 (27)
Buffered register set 1 (28)
30
Reg
26
26
26
26
26
Reg
27
Reg
28
SG1
YG1
7
7
7
7
7
Bit
7-6
5
4
3
2-0
Bit
7-0
Bit
7-0
Reserved
Name
Reserved
LDVIO
OPCKS
DPCEN
DPC
Name
SG1
Name
YG1
SG1
YG1
6
6
6
6
6
7-0
7-0
Active when BUFFER pin set HIGH.
Active when BUFFER pin set HIGH.
LDVIO
SG1
YG1
5
5
5
5
5
Description
Reserved, set to zero.
LDV clock select. LDV is an output when LOW and an input when HIGH
Output clock select. The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
Decoder product code
Read/Write in the TMC22153A only. Read-only in all other devices.
Description
Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar
lsb = 1/256
Description
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
lsb = 1/256
000
001
010
011
100
101
110
111
DPC
(continued)
OPCKS
SG1
YG1
4
4
4
Reserved
TMC22051A
TMC22052A
TMC22053A
Reserved
TMC22151A
TMC22152A
TMC22153A
4
4
DPCEN
SG1
YG1
3
3
3
3
3
Function
SG1
YG1
2
2
2
2
2
SG1
YG1
PRODUCT SPECIFICATION
DPC
1
1
1
1
1
REV. 1.0.0 2/4/03
SG1
YG1
0
0
0
0
0