AT43USB355M-AC ATMEL [ATMEL Corporation], AT43USB355M-AC Datasheet - Page 57

• Manufacturer Part Number: AT43USB355M-AC
• Description: Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
• Manufacturer: ATMEL [ATMEL Corporation]

2603G–USB–04/06
SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the
global interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If
SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and
SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master
mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low
when idle. Refer to Figure 20 and Figure 21 for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 20 or Figure 21 for the functionality of this bit.
• Bits 1,0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0
have no effect on the slave. The relationship between SCK and the Oscillator Clock frequency
f
Table 20. Relationship Between SCK and the Oscillator Frequency
CL
Initial Value
Read/Write
$0D ($2D)
is shown in the following table:
Bit
SPR1
0
0
1
1
SPIE
R/W
7
0
SPE
R/W
6
0
SPR0
DORD
R/W
5
0
0
1
0
1
MSTR
R/W
4
0
CPOL
R/W
3
0
CPHA
R/W
SCK Frequency
2
0
187.5 kHz
93.75 kHz
750 kHz
3 MHz
AT43USB355
SPR1
R/W
0
1
SPR0
R/W
0
0
SPCR
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