AT43USB355M-AC ATMEL [ATMEL Corporation], AT43USB355M-AC Datasheet - Page 32

• Manufacturer Part Number: AT43USB355M-AC
• Description: Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
• Manufacturer: ATMEL [ATMEL Corporation]

USB End-point
Interrupt Sources
32
AT43USB355
An assertion or activation of one or more bits in the end-point's Control and Status Register
triggers the end-point interrupts. These triggers are different for control and non-control end-
points as described in the table below. Please refer to the Control and Status Register for
more information.
Table 10. USB End-point Interrupt Sources
USB Interrupt Status Register – UISR
• Bit 7 – SOF INT: Start of Frame Interrupt
This bit is asserted after the USB hardware receives a valid SOF packet.
• Bit 6 – EOF2 INT: EOF2 Interrupt
This bit is asserted 10 clocks before the expected start of a frame.
• Bit 5 – Res: Reserved Bit
This bit is reserved and always reads as zero.
• Bit 4 – FEP3 INT: Function End-point 3 Interrupt
• Bit 3 – HEP0 INT: Hub End-point 0 Interrupt
• Bit 2 – FEP2 INT: Function End-point 2 Interrupt
• Bit 1 – FEP1 INT: Function End-point 1 Interrupt
• Bit 0 – FEP0 INT: Function End-point 0 Interrupt
The hub and function interrupt bits will be set by the hardware whenever the following bits in
the corresponding end-point's Control and Status Register are modified by the USB hardware:
1. RX OUT Packet is set (control and OUT end-points)
2. TX Packet Ready is cleared AND TX Complete is set (control and IN end-points)
3. RX SETUP is set (control end-points only)
4. TX Complete is set
Bit
RX_OUT_PACKET
TX_COMPLETE
STALL_SENT
RX_SETUP
Initial Value
Read/Write
$1FF7
Bit
SOF INT
R
7
0
EOF2 INT
R
6
0
R
5
–
0
FE3 INT
R
4
0
HEP0 INT
R
3
0
CONTROL, IN
End-point type
CONTROL, OUT
CONTROL, IN
CONTROL
FE2 INT
R
2
0
FE1 INT
R
1
0
FE0 INT
2603G–USB–04/06
R
0
0
UISR