PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 6

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

7
8
6.1
6.2
6.3
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8.1
6.3.1
6.3.2
6.3.3
6.3.4
RESET ............................................................................................................................................... 36
CONFIGURATION REGISTERS .................................................................................................. 41
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
8.1.10
8.1.11
8.1.12
8.1.13
8.1.14
8.1.15
8.1.16
8.1.17
8.1.18
8.1.19
8.1.20
8.1.21
8.1.22
8.1.23
8.1.24
8.1.25
8.1.26
8.1.27
8.1.28
8.1.29
8.1.30
8.1.31
8.1.32
8.1.33
8.1.34
8.1.35
8.1.1.1
PRIMARY AND SECONDARY CLOCK INPUTS ................................................................. 34
CLOCK JITTER........................................................................................................................ 34
MODE AND CLOCK FREQUENCY DETERMINATION ..................................................... 34
PRIMARY INTERFACE RESET ............................................................................................. 37
SECONDARY INTERFACE RESET ....................................................................................... 37
BUS PARKING & BUS WIDTH DETERMINATION............................................................. 38
SECONDARY DEVICE MASKING........................................................................................ 38
ADDRESS PARITY ERRORS ................................................................................................. 39
OPTIONAL BASE ADDRESS REGISTER ............................................................................. 39
OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS........................ 39
SHORT TERM CACHING ....................................................................................................... 40
CONFIGURATION REGISTER SPACE MAP........................................................................ 41
PRIMARY BUS ..................................................................................................................... 34
SECONDARY BUS ............................................................................................................... 35
CLOCK STABILITY.............................................................................................................. 36
DRIVER IMPEDANCE SELECTION................................................................................... 36
VENDOR ID REGISTER – OFFSET 00h............................................................................. 42
DEVICE ID REGISTER – OFFSET 00h .............................................................................. 42
COMMAND REGISTER – OFFSET 04h.............................................................................. 42
PRIMARY STATUS REGISTER – OFFSET 04h .................................................................. 43
REVISION ID REGISTER – OFFSET 08h ........................................................................... 44
CLASS CODE REGISTER – OFFSET 08h........................................................................... 44
CACHE LINE SIZE REGISTER – OFFSET 0Ch ................................................................. 44
PRIMARY LATENCY TIMER – OFFSET 0Ch ..................................................................... 44
HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 44
BIST REGISTER – OFFSET 0Ch .................................................................................... 44
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h .................................. 45
UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h................................... 45
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................... 45
SECONDARY BUS NUMBER REGISTER – OFFSET 18h ............................................. 45
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ......................................... 45
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................ 45
I/O BASE ADDRESS REGISTER – OFFSET 1Ch........................................................... 46
I/O LIMIT REGISTER – OFFSET 1Ch............................................................................ 46
SECONDARY STATUS REGISTER – OFFSET 1Ch ....................................................... 46
MEMORY BASE REGISTER – OFFSET 20h .................................................................. 47
MEMORY LIMIT REGISTER – OFFSET 20h ................................................................. 47
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h.................................... 47
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h................................... 47
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h............................ 47
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch.......................... 48
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h.................................................... 48
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h .................................................. 48
CAPABILITY POINTER – OFFSET 34h ......................................................................... 48
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h .................................. 48
INTERRUPT LINE REGISTER – OFFSET 3Ch.............................................................. 48
INTERRUPT PIN REGISTER – OFFSET 3Ch ................................................................ 48
BRIDGE CONTROL REGISTER – OFFSET 3Ch ........................................................... 49
PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h........................ 50
SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h.................. 51
SIGNAL TYPE DEFINITION................................................................................................... 42
Page 6 of 77
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100