PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 49

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.33
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
31:28
27
26
25
24
23
22
21
20
19
18
17
FUNCTION
RESERVED
Discard Timer
P_SERR# Enable
Master Timeout Status
Secondary Master
Timeout Status
Primary Master Timeout
Status
Fast Back-to-Back
Secondary Interface
Reset
Master Abort Mode
RESERVED
VGA Enable
ISA Enable
S_SERR# Enable
TYPE
RO
RO
RW
RW
RWC
RW
RW
RW
RW
RO
RW
RW
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DESCRIPTION
Reserved. Returns 0h when read.
Discard Timer P_SERR# Enable
0: Does not assert P_SERR# on the primary interface as a result of
the expiration of either the primary discard timer or secondary
discard timer.
1: Asserts P_SERR# on the primary interface as a result of the
expiration of either the primary discard timer or secondary discard
timer.
This bit is ignored in PCI-X mode. Reset to 0h.
Master Timeout Status
0: No discard timer error
1: Discard timer error (from primary or secondary discard timer)
This bit remains 0 when in PCI-X mode. Reset to 0h.
Secondary Master Timeout Status
0: The secondary discard timer counts 2
1: The secondary discard timer counts 2
If the secondary interface is in PCI-X mode, this bit is ignored.
Reset to 0h.
Primary Master Timeout Status
0: The primary discard timer counts 2
1: The primary discard timer counts 2
If the primary interface is in PCI-X mode, this bit is ignored. Reset
to 0h.
Fast Back-to-Back Transaction Enable
Designates PI7C21P100 does not generate fast back-to-back
transactions. Returns 0 when read.
Secondary Interface Reset
0: Does not force the assertion of S_RST# on the secondary interface
1: Forces the assertion of S_RST# on the secondary interface.
Reset to 0h.
Master Abort Mode
0: Do not report master aborts. Returns FFFFFFFFh on reads and
discard data on writes.
1: Report master aborts by signaling target abort if possible or by
asserting SERR# (if enabled).
If in PCI-X mode, PI7C21P100 will return a split completion
message, leaving the host bridge to return FFFFFFFFh on any non-
posted transaction when the non-posted transaction ends in a master
abort.
Reset to 0h.
Reserved. Returns 0 when read.
VGA Enable
0: Does not forward VGA compatible memory and I/O addresses
from the primary to secondary interface unless they are enabled for
forwarding by the defined I/O and memory address ranges.
1: Forwards VGA compatible memory and I/O addresses from the
primary to secondary interface (if the I/O enable and Memory enable
bits are set) independent of the defined I/O and memory address
ranges and independent of the ISA enable bit.
ISA Enable
0: Forward downstream all I/O addresses in the address defined by
the I/O base and limit registers.
1: Forward upstream all I/O addresses in the address range defined
by the I/O base and limit registers that are in the first 64KB of PCI
I/O address space
Reset to 0h.
S_SERR# Enable
0: Disable the forwarding of S_SERR# to P_SERR#
1: Enable the forwarding of S_SERR# to P_SERR#.
Reset to 0h.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
15
10
15
10
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
PCI clock cycles.
PI7C21P100