PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 28

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

4.3.4
4.3.5
4.3.5.1
4.3.5.2
NON-PREFETCHABLE AND DWORD READS
A non-prefetchable read transaction is a read transaction in which PI7C21P100 requests
exactly one DWORD from the target and disconnects the initiator after delivering that one
DWORD of read data. Unlike prefetchable read transactions, PI7C21P100 forwards the read
byte enable information for the data phase. Non-prefetchable behavior is used for I/O,
configuration, memory read transactions that fall into the nonprefetchable memory space for
PCI mode, and all DWORD read transactions in PCI-X mode.
PREFETCHABLE READS
A prefetchable read transaction is a read transaction where PI7C21P100 performs speculative
reads, transferring data from the target before it is requested from the initiator. This behavior
allows a prefetchable read transaction to consist of multiple data transfers. For prefetchable
read transactions, all byte enables are asserted for all data phases.
Prefetchable behavior is used for memory read line and memory read multiple transactions, as
well as for memory read transactions that fall into prefetchable memory space and are allowed
to fetch more than a DWORD. The amount of data that is prefetched depends on the type of
transaction and the setting of bits in the primary and secondary data buffering control registers
in configuration space. The amount of prefetching may also be affected by the amount of free
buffer space available in PI7C21P100, and by any read address boundaries encountered.
For PCI-X to PCI transactions, PI7C21P100 continues to generate data requests to the PCI
interface and keeps the prefetch buffer full until the entire amount of data requested is
transferred.
For PCI-X to PCI-X transactions, the split transaction commitment limit value contained in
the upstream or downstream split transaction register determines the operation. If the value is
greater than or equal to the split transaction capacity (4KB) but less than 32KB, the maximum
request amount is 512 bytes. Larger transfers will be decomposed into a series of smaller
transfers, until the original byte count has been satisfied. If the commitment limit value
indicates 32KB or more, the original request amount is used and decomposition is not
performed.
If the original request is broken into smaller requests the bridge waits until the previous
completion has been totally received before a new request is issued. This ensures that the data
does not get out of order and that two requests with the same sequence ID are not issued. In
either case, the bridge generates a new requester ID for each request passed through the
bridge.
The method used for transfers in PCI-to-PCI mode is user defined in the primary and
secondary data buffering control registers. These registers have bits for memory read to
prefetchable space, memory read line, and memory read multiple transactions. For memory
read, the bits select whether to read a DWORD, read to a cache line boundary, or to fill the
prefetch buffer. For memory read line and memory read multiple transactions, the bits select
whether to read to a cache line boundary or to fill the prefetch buffer. In all cases, if the bits
PCI-X TO PCI-X AND PCI-X TO PCI
PCI TO PCI
Page 28 of 77
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100