AD7829 AD [Analog Devices], AD7829 Datasheet - Page 7

• Manufacturer Part Number: AD7829
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs
• Manufacturer: AD [Analog Devices]

Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2, when Switch 2 is in Posi-
tion A. At the point when the track-and-hold returns to its track
mode, this signal is sampled by the sampling capacitor as Switch 2
moves into Position B. The first flash occurs at this instant and
is then followed by the second flash. Typically, the first flash is
complete after 100 ns, i.e., at 220 ns, while the end of the second
flash and hence the 8-bit conversion result is available at 330 ns
(minimum). The maximum conversion time is 420 ns. As shown
in Figure 4, the track-and-hold returns to track mode after 120 ns,
and starts the next acquisition before the end of the current
conversion. Figure 6 shows the ADC transfer function.
REV. B
V
V
IN
IN
T/H 1
T/H 1
REFERENCE
REFERENCE
HOLD
HOLD
A
A
TIMING AND
TIMING AND
SW2
CONTROL
SW2
CONTROL
B
Figure 3. ADC Conversion Phase
Figure 2. ADC Acquisition Phase
B
LOGIC
LOGIC
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
R14
R13
R16
R14
R13
R15
R16
R15
R1
R1
13
15
14
13
15
14
1
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
–7–
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7822,
AD7825, and AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (EOC) idles high, the falling edge of CONVST
initiates a conversion and at the end of conversion the falling
edge of EOC is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel Interface section for
more details.) V
such as the AD780, while V
that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input
section.) When V
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the EOC pin on the AD7822 and
AD7825 equal to a low. Ensure the CONVST line is not floating
when V
AD7829 into an unknown state. A suggestion is to tie CONVST
to V
edge on the CONVST pin will cause the AD7829 to fully power up
while a rising edge on the PD pin will cause the AD7822 and
AD7825 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power performance.
(See Power-Down Options section of the data sheet.)
DB0–DB7
CONVST
4.5V TO 5.5V
DD
EOC
CS
RD
SUPPLY
or DGND through a pull-up or pull-down resistor. A rising
DD
TRACK
3.75V INPUT
1.25V TO
is applied, as this could put the AD7822/AD7825/
Figure 5. Typical Connection Diagram
Figure 4. Track-and-Hold Timing
t
10 F
2
REF
DD
120ns
HOLD
is first connected, the AD7822, AD7825, and
and V
AD7822/AD7825/AD7829
t
1
V
V
AGND
V
DGND
0.1 F
IN1
IN2
IN4(8)
MID
DD
V
are connected to a voltage source
DD
is connected to a voltage source
AD7822/
AD7825/
AD7829
AD780
2.5V
V
REF
TRACK
DB0–DB7
CONVST
V
VALID
DATA
MID
EOC
RD
CS
PD
A0
A2
A1
INTERFACE
PARALLEL
t
3
HOLD
C/ P