AD7829 AD [Analog Devices], AD7829 Datasheet - Page 15

• Manufacturer Part Number: AD7829
• Description: 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel Sampling ADCs
• Manufacturer: AD [Analog Devices]

Interfacing Multiplexer Address Inputs
Figure 26 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The mul-
tiplexer address is latched on the falling edge of the RD signal,
as outlined in the Parallel Interface section, which allows the use
of the 3 LSBs of the address bus to select the channel address.
As shown in Figure 26, only address bits A3 to A15 are address
decoded allowing A0 to A2 to be changed according to desired
channel selection without affecting chip selection.
REV. B
AD7822
CONVST
DB7–DB0
A15–A3
EOC
RD
CS
ADDRESS
DECODE
Figure 26. AD7825/AD7829 Simplified Microinterfacing Scheme
Figure 27. AD7822 Stand-Alone Operation
CS
RD
DB7–DB0
A0
A1
A2
LATCH/ASIC
DSP/
AD7825/
AD7829
DB0–DB7
–15–
A15–A3
A2–A0
DB0–DB7
CONVST
RD
CS
EOC
AD7822 Stand–Alone Operation
The AD7822, being the single channel device, does not have
any multiplexer addressing associated with it and can in fact be
controlled with just one signal, i.e., the CONVST signal. As
shown in Figure 27, the RD and CS pins are both tied to the
EOC pin, and the resulting signal may be used as an interrupt
request signal (IRQ) on a DSP, as a WR signal to memory, or as
a CLK to a latch or ASIC. The timing for this interface,
as shown in Figure 27, demonstrates how with the CONVST
signal alone, a conversion may be initiated, data is latched out,
and the operating mode of the AD7822 can be selected.
CS
RD
MICROPROCESSOR READ CYCLE
(CHANNEL SELECTION A0–A2)
t
1
MUX ADDRESS
LATCHED
AD7822/AD7825/AD7829
ADC I/O ADDRESS
MUX ADDRESS
A/D RESULT
A/D RESULT
t
4