AD7829 AD [Analog Devices], AD7829 Datasheet
AD7829
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AD7829 Summary of contents
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... IC (SOIC) and a 20-/24-lead thin shrink small outline package (TSSOP). The AD7829 is available in a 28-lead 0.6" wide, plastic dual-in-line package (DIP), a 28-lead small outline IC (SOIC) and in a 28-lead thin shrink small outline package (TSSOP). ...
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... AD7822/AD7825/AD7829–SPECIFICATIONS V = 2.5 V. All specifications – +85 C unless otherwise noted.) REF IN/OUT Parameter DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio 1 Total Harmonic Distortion 1 Peak Harmonic or Spurious Noise 1 Intermodulation Distortion 2nd Order Terms 3rd Order Terms 1 Channel-to-Channel Isolation DC ACCURACY Resolution Minimum Resolution for Which ...
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... Typically 24 mW 9.58 mW typ 23.94 mW typ Model AD7822BN AD7822BR 2.1V AD7822BRU AD7825BN AD7825BR AD7825BRU AD7829BN AD7829BR AD7829BRU –3– AD7822/AD7825/AD7829 ORDERING GUIDE Linearity Package Package Error Description Option ± 0.75 LSB Plastic DIP N-20 ± 0.75 LSB Small Outline IC R-20 ± 0.75 LSB Thin Shrink Small RU-20 Outline (TSSOP) ± ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, perma- nent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Parallel Inter- face section of this data sheet.) CS Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829. This is necessary if the ADC is sharing a common data bus with another device. PD Logic Input ...
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... It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected V AD7825/AD7829. It means that the user must wait for the dura- tion of the track/hold acquisition time after a channel change/step input change to V ensure that the part operates to specification ...
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... V or DGND through a pull-up or pull-down resistor. A rising DD edge on the CONVST pin will cause the AD7829 to fully power up while a rising edge on the PD pin will cause the AD7822 and AD7825 to fully power up. For applications where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance ...
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... AD7822/AD7825/AD7829 ADC TRANSFER FUNCTION The output coding of the AD7822, AD7825, and AD7829 is straight binary. The designed code transitions occur at succes- sive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size /256 ( the LSB size = (0.8 V REF V). The ideal transfer characteristic for the AD7822, DD AD7825, and AD7829 is shown in Figure 6, below ...
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... V ± 2%. Analog Input Structure Figure 11 shows an equivalent circuit of the analog input structure of the AD7822, AD7825, and the AD7829. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV ...
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... This is the 13 the on-chip reference. When V AD7825, and AD7829 are in a low current mode of operation. Ensure that the CONVST line is not floating when there is a glitch on CONVST while V attempt to power up before V an unknown state ...
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... CONVST pin, a rising edge on either the PD pin or the CONVST pin will power the part up again. As with the AD7829, when using an external reference with the AD7822 or AD7825, the falling edge of CONVST may occur before the required power-up time has elapsed, however, if this ...
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... The ADC is powered up again on the rising edge of the CONVST signal. Superior power performance can be achieved in this mode of operation by only powering up the AD7822, AD7825, and AD7829 to carry out a conversion. The parallel interface of the AD7822, AD7825, and AD7829 is still fully operational while the ADCs are powered down. A read may occur while the part is powered down, and so it does not necessarily need to be placed within the EOC pulse as shown in Figure 21 ...
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... ASIC, this EOC pulse can be applied to the CS and RD inputs to latch data out of the AD7822, AD7825, and AD7829 and into the gate array or ASIC. This means that the gate array or ASIC does not need any conver- sion status recognition logic and it also eliminates the logic required in the gate array or ASIC to generate the read signal for the AD7822, AD7825, and AD7829 ...
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... Port 2. Port 2 latches remain stable when the AD7822, AD7825, and AD7829 are addressed, as they do not have to be turned around (set to 1) for data input as is the case for Port 0. ...
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... Interfacing Multiplexer Address Inputs Figure 26 shows a simplified interfacing scheme between the AD7825/AD7829 and any microprocessor or microcontroller, which facilitates easy channel selection on the ADCs. The mul- tiplexer address is latched on the falling edge of the RD signal, as outlined in the Parallel Interface section, which allows the use of the 3 LSBs of the address bus to select the channel address ...
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... AD7822/AD7825/AD7829 0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP (N-20) 1.060 (26.90) 0.925 (23.50 0.280 (7.11) 0.240 (6.10 PIN 1 0.060 (1.52) 0.015 (0.38) MAX 0.130 (3.30) MIN SEATING 0.022 (0.558) 0.100 0.070 (1.77) PLANE (2.54) 0.014 (0.356) 0.045 (1.15) BSC 20-Lead Small Outline Package (R-20) 0 ...
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... Thin Shrink Small Outline Package (RU-24) 0.311 (7.90) 0.303 (7.70 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) –17– AD7822/AD7825/AD7829 0.325 (8.25) 0.195 (4.95) 0.300 (7.62) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0291 (0.74) x 45° 0.0098 (0.25) 0.0500 (1.27) 8° 0° 0.0157 (0.40) 0.028 (0.70) 8° 0° 0.020 (0.50) ...
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... AD7822/AD7825/AD7829 0.250 (6.35) MAX 0.200 (5.05) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Plastic DIP (N-28) 1.565 (39.70) 1.380 (35.10 0.580 (14.73) 0.485 (12.32 0.625 (15.87) 0.600 (15.24) 0.060 (1.52) PIN 1 0.015 (0.38) 0.150 (3.81) MIN 0.022 (0.558) 0.070 0.100 SEATING (2.54) (1.77) 0.014 (0.356) PLANE ...
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... Edit to POWER REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edit to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edit to CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edit toTYPICAL CONNECTION DIAGRAM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Edit to ANALOG INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edit to ANALOG INPUT SELECTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edit to POWER-UP TIMES section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to POWER vs. THROUGHPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AD7822 Stand-Alone Operation section created . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REV. B AD7822/AD7825/AD7829 –19– Page ...
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