AD5412ACPZ AD [Analog Devices], AD5412ACPZ Datasheet - Page 8

• Manufacturer Part Number: AD5412ACPZ
• Description: Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
• Manufacturer: AD [Analog Devices]

AD5412/AD5422
TIMING CHARACTERISTICS
AV
DV
all specifications T
Table 4.
Parameter
Write Mode
Readback Mode
Daisychain Mode
1
2
3
4
Guaranteed by characterization. Not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
C
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
L SDO
DD
CC
= Capacitive load on SDO output.
= 10.8V to 40V, AV
= 2.7 V to 5.5 V, V
1, 2, 3
MIN
to T
Limit at T
33
13
13
13
40
5
5
5
40
20
5
82
33
33
13
40
5
5
40
40
82
33
33
13
40
5
5
40
40
33
OUT
SS
MAX
= -26.4V to -3V/0V, AV
: R
, ±10 V / 0 to 24 mA range unless otherwise noted.
R
L
= t
= 1 kΩ, C
MIN
F
= 5 ns (10% to 90% of DV
, T
MAX
L
= 200 pF, I
DD
Unit
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns min
ns min
µs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
+ |AV
OUT
CC
) and timed from a voltage level of 1.2 V.
: R
SS
Rev. PrF | Page 8 of 38
L
| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
= 300Ω, H
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
LATCH high time (After a write to the CONTROL register)
Data setup time
Data hold time
LATCH low time
CLEAR pulsewidth
CLEAR activation time
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
LATCH rising edge to SDO tri-state
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
L
= 50mH;
L SDO
L SDO
Preliminary Technical Data
4
4
= 15pF)
= 15pF)