AD5412ACPZ AD [Analog Devices], AD5412ACPZ Datasheet - Page 25

• Manufacturer Part Number: AD5412ACPZ
• Description: Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of
SCLK. The input register consists of 8 address bits and 16 data
bits as shown in Table 7. The 24 bit word is unconditionally
Table 7. Input Shift Register Format
MSB
D23
Table 8. Control Word Functions
Address Word
00000000
00000001
00000010
01010101
01010110
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The rising edge of SCLK that clocks in the MSB of the
dataword marks the beginning ot the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24
SCLK edge, the data written will be invalid. If more than 24
rising SCLK edges are applied before LATCH is brought high,
the input data will also be invalid.
D22
D21
ADDRESS WORD
No Operation (NOP)
DATA Register
Readback register value as per Read Address
(See Table 10)
CONTROL Register
RESET Register
Function
D20
D19
D18
D17
D16
D15
th
rising
D14
Rev. PrF | Page 25 of 38
D13
D12
latched on the rising edge of LATCH. Data will continue to be
clocked in irrespective of the state of LATCH, on the rising edge
of LATCH the data that is present in the input register will be
latched, in other words the last 24 bits to be clocked in before
the rising edge of LATCH is the data that is latched. The timing
diagram for this operation is shown in Figure 2.
D11
CONTROLLER
SERIAL CLOCK
CONTROL OUT
D10
DATA IN
Figure 60. Daisy Chaining the AD5412/AD5422
DATA OUT
*ADDITIONAL PINS OMITTED FOR CLARITY
D9
DATA WORD
D8
D7
D6
D5
AD5412/AD5422
SDIN
SCLK
LATCH
SCLK
LATCH
SCLK
LATCH
D4
AD5422*
AD5422*
AD5422*
AD5412/
AD5412/
AD5412/
SDIN
SDIN
SDO
SDO
SDO
D3
D2
D1
LSB
D0