AD5412ACPZ AD [Analog Devices], AD5412ACPZ Datasheet - Page 11

• Manufacturer Part Number: AD5412ACPZ
• Description: Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
TSSOP Pin No.
1
2
3
4,12
18
5
6
7
8
9
10
11
N/A
13
14
15
16
17
LFCSP Pin No.
14,37
39
2
3,15
1,10,11,19,
20,21,22,25,30,
31,35,38,40
4
5
6
7
8
9
12
13
16
17
18
23
24
CLEAR SELECT
CLEAR
FAULT
LATCH
Figure 5. TSSOP Pin Configuration
AGND
SCLK
DV
AV
SDIN
GND
SDO
GND
CC
SS
Mnemonic
AV
DV
FAULT
GND
NC
CLEAR
SELECT
CLEAR
LATCH
SCLK
SDIN
SDO
AGND
DGND
R
REFOUT
REFIN
DV
SELECT
C
10
11
12
1
2
3
4
5
6
7
8
9
SET
COMP
SS
CC
CC
(Not to Scale)
TOP VIEW
AD5412/
AD5422
Description
Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Fault alert, This pin is asserted low when an open circuit is detected in current mode or
an over temperature is detected. Open drain output, must be connected to a pull-up
resistor.
These pins must be connected to 0V.
No Connection. Do not connect to this pin.
Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 21
Active High Input. Asserting this pin will set the current output to the bottom of the
selected range or will set the voltage output to the user selected value (zero-scale or
mid-scale).
Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This
operates at clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback
mode. Data is valid on the rising edge of SCLK . See Figure 3 and Figure 4.
Ground reference pin for analog circuitry.
Ground reference pin for digital circuitry. (AGND and DGND are internally connected in
TSSOP package).
An external, precision, low drift 15kΩ current setting resistor can be connected to this
pin to improve the I
Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for
specified performance.
This pin when connected to GND disables the internal supply and an external supply
must be connected to the DV
supply. Refer to features section.
Optional compensation capacitor connection for the voltage output buffer. Connecting
a 4nF capacitor between this pin and the V
up to 1µF. It should be noted that the addition of this capacitor will reduce the
24
23
22
21
20
19
18
17
16
15
14
13
V
-V
+V
BOOST
REFIN
I
NC
DV
REFOUT
R
AV
C
OUT
OUT
COMP
SET
SENSE
SENSE
DD
CC
SELECT
Rev. PrF | Page 11 of 38
CLEAR SELECT
OUT
temperature drift performance. Refer to Features section.
CLEAR
FAULT
LATCH
SCLK
SDIN
GND
SDO
NC
NC
Figure 6. LFCSP Pin Configuration
10
1
2
3
4
5
6
7
8
9
CC
40
11
pin. Leave this pin unconnected to enable the internal
12
39
13
38
14
37
(Not to Scale)
AD5412/
AD5422
TOP VIEW
36
15
OUT
16
35
34
17
pin will allow the voltage output to drive
33
18
19
32
31
20
30
29
28
27
26
25
24
23
22
21
NC
CAP2
CAP1
BOOST
I
NC
C
DV
NC
NC
OUT
COMP
CC
SELECT
AD5412/AD5422