AD5412ACPZ AD [Analog Devices], AD5412ACPZ Datasheet - Page 30

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AD5412ACPZ

Manufacturer Part Number
AD5412ACPZ
Description
Single Channel, 12/16-Bit, Serial Input, Current Source & Voltage Output DAC
Manufacturer
AD [Analog Devices]
Datasheet

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AD5412/AD5422
FEATURES
FAULT ALERT
The AD5412/AD5422 is equipped with a FAULT pin, this is an
open-drain output allowing several AD5412/AD5422 devices to
be connected together to one pull-up resistor for global fault
detection. The FAULT pin is forced active by any one of the
following fault scenarios;
The I
are used in conjunction with the FAULT pin to inform the user
which one of the fault conditions caused the FAULT pin to be
asserted. See Table 19 and Table 20.
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation the voltage output will sink/source
10mA and maintain specified operation. The maximum current
that the voltage output will deliver is approx. 20mA, this is the
short circuit current.
VOLTAGE OUTPUT OVER-RANGE
An over-range facility is provided on the voltage output. When
enabled via the CONTROL register, the selected output range
will be over-ranged by 10%.
VOLTAGE OUTPUT FORCE-SENSE
The +V
sensing of the load connected to the voltage output. If the load
is connected at the end of a long or high impedance cable,
sensing the voltage at the load will allow the output amplifier to
compensate and ensure the correct voltage is applied across the
load. This function is limited only by the available power supply
headroom.
1)
2)
OUT
SENSE
FAULT and OVER TEMP bits of the STATUS register
The Voltage at I
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The I
controlled by a PMOS transistor and internal
amplifier as shown in Figure 58. The internal circuitry
that develops the fault output avoids using a
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approxiamately one volt of remaining drive
capability (when the gate of the output PMOS
transistor nearly reaches ground). Thus the FAULT
output activates slightly before the compliance limit is
reached. Since the comparison is made within the
feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain and an
output error does not occur before the FAULT output
becomes active.
If the core temperature of the AD5412/AD5422
exceeds approx. 150°C.
and –V
SENSE
pins are provided to facilitate remote
OUT
attempts to rise above the
OUT
current is
Rev. PrF | Page 30 of 38
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the voltage output to
be cleared to either zero-scale code or mid-scale code, user-
selectable via the CLEAR SELECT pin or the CLRSEL bit of the
CONTROL register as described in Table 21. (The Clear select
feature is a logical OR function of the CLEAR SELECT pin and
the CLRSEL bit). The Current output will clear to the bottom of
its programmed range. It is necessary to maintain CLEAR high
for a minimum amount of time (see Figure 2) to complete the
operation. When the CLEAR signal is returned low, the output
remains at the cleared value.The pre-clear value can be restored
by pulsing the LATCH signal low without clocking any data. A
new value cannot be programmed until the CLEAR pin is
returned low.
Table 21. CLEAR SELECT Options
CLRSEL
0
1
As well as defining the output value for a clear operation, the
CLRSEL bit and CLEAR SELECT pin also define the default
output value. On selection of a new voltage range the output
value will be as defined in Table 21. It is recommended, to avoid
glitches on the output, that before changing voltage ranges the
output be disabled by setting the OUTEN bit of the Control
register to logic low. When OUTEN is set to logic high the
output will go to the default value as defined by CLRSEL and
CLEAR SELECT.
INTERNAL REFERENCE
The AD5412/AD5422 contains an integrated +5V voltage
reference with initial accuracy of ±2mV max and a temperature
drift coefficient of ±10 ppm/°C max. The reference voltage is
buffered and externally available for use elsewhere within the
system. See Figure 56 for a load regulation graph of the
Integrated reference.
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 58, R1 is an internal sense resistor as part of
the voltage to current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of R1. As a method of improving the stability of the
output current over temperature an external precision 15kΩ low
drift resistor can be connected to the R
AD5412/AD5422 to be used instead of the internal resistor R1.
The external resistor is selected via the CONTROL register. See
Table 14.
DIGITAL POWER SUPPLY
By default, the DV
alternatively, via the DV
supply may be output on the DV
Unipolar Output Range
0 V
Mid-Scale
CC
Preliminary Technical Data
pin accepts a power supply of 2.7V to 5.5V,
CC
SELECT pin an internal 4.5V power
Output Value
CC
pin for use as a digital power
SET
pin of the
Bipolar Output Range
0 V
Negative Full-Scale

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