gvt71256d36 ETC-unknow, gvt71256d36 Datasheet - Page 4

• Manufacturer Part Number: gvt71256d36
• Description: 256k 36/512k Synchronous Sram
• Manufacturer: ETC-unknow

256K X 36 PIN DESCRIPTION S
May 18, 199 9
Rev. 5/99
GALVANTECH
2C, 3C, 5C, 6C, 2R, 6R, 3T,
3D, 5D, 3E, 5E, 3F, 5F, 3H,
1B, 7B, 1C, 7C, 4D, 3J, 5J,
4L, 1R, 5R, 7R, 1T, 2T, 6T,
6U
2A, 3A, 5A, 6A, 3B, 5B, 6B,
(a) 6P, 7P, 7N, 6N, 6M, 6L,
(b) 7H, 6H, 7G, 6G, 6F, 6E,
(c) 2D, 1D, 1E, 2E, 2F, 1G,
(d) 1K, 2K, 1L, 2L, 2M, 1N,
1A, 7A, 1F, 7F, 1J, 7J, 1M,
- (not available for PBGA)
5H, 3K, 5K, 3M, 5M, 3N,
X36 PBGA PIN S
4C, 2J, 4J, 6J, 4R
2G, 1H, 2H,
7E, 7D, 6D,
7L, 6K, 7K,
7M, 1U, 7U
2N, 1P, 2P
5N, 3P, 5P
4T, 5T
5G
3G
4M
4G
4P
4N
5L
3L
4H
4K
4E
2B
4F
4A
4B
3R
7T
2U
3U
4U
5U
99, 82, 81, 44, 45, 46,
14, 16, 66
38, 39, 42 for TA
Version
(a) 51, 52, 53, 56, 57,
(b) 68, 69, 72, 73, 74,
(d) 18, 19, 22, 23, 24,
55, 60, 67, 71, 76, 90
5, 10, 17, 21, 26, 40,
4, 11, 20, 27, 54, 61,
(c) 1, 2, 3, 6, 7, 8, 9,
X36 QFP PIN S
35, 34, 33, 32, 100,
for B and T version
for B and T version
92 (for TA Version
43 (TA Version)
92 (T Version)
47, 48, 49, 50
58, 59, 62, 63
75, 78, 79, 80
25, 28, 29, 30
15, 41,65, 91
12, 13
70, 77
only)
37
36
93
94
95
96
87
88
89
98
97
86
83
84
85
31
64
38
39
43
42
SYMBOL
ADSP#
ADSC#
, INC.
MODE
VCCQ
BWE#
BWa#
BWb#
BWc#
BWd#
ADV#
CE2#
GW#
TMS
TDO
VCC
CLK
CE#
CE2
OE#
DQa
DQb
DQc
DQd
TCK
VSS
TDI
NC
A0
A1
ZZ
A
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronou
I/O Supply
TYPE
Ground
Output
Output
Supply
Input-
Input-
Input-
Input-
Input-
Input-
input-
input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Input
Input
s
-
256K X 36/512K X 18 SYNCHRONOUS SRAM
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CLK. The burst counter generates internal addresses
associated with A0 and A1, during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BWa# controls DQa. BWb# controls DQb. BWc# controls DQc. BWd# controls
DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by
BWE# being LOW.
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit WRITE to occur
independent of the BWE# and BWn# lines and must meet the setup and hold times
around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device and to gate
ADSP#.
Chip enable: This active HIGH input is used to enable the device.
Chip enable: This active LOW input is used to enable the device. Not available for B
and T package versions.
Output Enable: This active LOW asynchronous input enables the data output
drivers.
Address Advance: This active LOW input is used to control the internal burst
counter. A HIGH on this pin generates wait cycle (no address advance).
Address Status Processor: This active LOW input, along with CE# being LOW,
causes a new external address to be registered and a READ cycle is initiated using
the new address.
Address Status Controller: This active LOW input causes device to be de-selected
or selected along with new external address to be registered. A READ or WRITE
cycle is initiated depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR
BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
Snooze: This active HIGH input puts the device in low power consumption standby
mode. For normal operation, this input has to be either LOW or NC (No Connect).
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb. Third Byte is DQc.
Fourth Byte is DQd. Input data must meet setup and hold times around the rising
edge of CLK.
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not available for TA package version.
Core power Supply: +3.3V -5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected. User can leave it floating
or connect it to VCC or VSS.
4
GVT71256D36/GVT71512D18
Galvantech, Inc. reserves the right to change products or specifications without notice
DESCRIPTIO N
.