gvt71256d36 ETC-unknow, gvt71256d36 Datasheet - Page 15

• Manufacturer Part Number: gvt71256d36
• Description: 256k 36/512k Synchronous Sram
• Manufacturer: ETC-unknow

IEEE 1149.1 SERIAL BOUNDARY
SCAN (JTAG)
OVERVIEW
port (TAP). This port is designed to operate in a manner
consistent with IEEE Standard 1149.1-1990 (commonly
referred to as JTAG), but does not implement all of the
functions required for IEEE 1149.1 compliance. Certain
functions have been modified or eliminated because their
implementation places extra delays in the critical speed path
of the device. Nevertheless, the device supports the standard
TAP controller architecture (the TAP controller is the state
machine that controls the TAPs operation) and can be
expected to function in a manner that does not conflict with
the operation of devices with IEEE Standard 1149.1
compliant TAPs. The TAP operates using LVTTL/LVCMOS
logic level signaling.
DISABLING THE JTAG FEATUR E
feature. To disable the TAP controller without interfering with
normal operation of the device, TCK should be tied LOW
(VSS) to prevent clocking the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be pulled up to VCC through a resistor. TDO
should be left unconnected. Upon power-up the device will
come up in a reset state which will not interfere with the
operation of the device.
TEST ACCESS PORT (TAP )
TCK - TEST CLOCK (INPUT )
rising edge of TCK and all outputs propagate from the falling
edge of TCK.
TMS - TEST MODE SELECT (INPUT )
This is the command input for the TAP controller state
machine. It is allowable to leave this pin unconnected if the
TAP is not used. The pin is pulled up internally, resulting in a
logic HIGH level.
TDI - TEST DATA IN (INPUT )
is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is
May 18, 199 9
Rev. 5/99
GALVANTECH
This device incorporates a serial boundary scan access
It is possible to use this device without using the JTAG
Clocks all TAP events. All inputs are captured on the
The TMS input is sampled on the rising edge of TCK.
The TDI input is sampled on the rising edge of TCK. This
, INC.
256K X 36/512K X 18 SYNCHRONOUS SRAM
15
determined by the state of the TAP controller state machine
and the instruction that is currently loaded in the TAP
instruction register (refer to Figure 3, TAP Controller State
Diagram). It is allowable to leave this pin unconnected if it is
not used in an application. The pin is pulled up internally,
resulting in a logic HIGH level. TDI is connected to the most
significant bit (MSB) of any register. (See Figure 4.)
TDO - TEST DATA OUT (OUTPUT )
from the registers. The output that is active depending on the
state of the TAP state machine (refer to Figure 3, TAP
Controller State Diagram). Output changes in response to the
falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO. TDO is connected to
the least significant bit (LSB) of any register. (See Figure 4.)
PERFORMING A TAP RESE T
which is optional in the IEEE 1149.1 specification). A
RESET can be performed for the TAP controller by forcing
TMS HIGH (VCC) for five rising edges of TCK and pre-
loads the instruction register with the IDCODE command.
This type of reset does not affect the operation of the system
logic. The reset affects test logic only.
TDO is in a High-Z state.
TEST ACCESS PORT (TAP)
REGISTERS
OVERVIEW
the sequences of ones and zeros input to the TMS pin as the
TCK is strobed. Each of the TAPs registers are serial shift
registers that capture serial input data on the rising edge of
TCK and push serial data out on subsequent falling edge of
TCK. When a register is selected, it is connected between the
TDI and TDO pins.
INSTRUCTION REGISTE R
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions are
three bits long. The register can be loaded when it is placed
between the TDI and TDO pins. The parallel outputs of the
instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the
The TDO output pin is used to serially clock data-out
The TAP circuitry does not have a reset pin (TRST#,
At power-up, the TAP is reset internally to ensure that
The various TAP registers are selected (one at a time) via
The instruction register holds the instructions that are
GVT71256D36/GVT71512D18
Galvantech, Inc. reserves the right to change products or specifications without notice
.