gvt71256d36 ETC-unknow, gvt71256d36 Datasheet - Page 17

• Manufacturer Part Number: gvt71256d36
• Description: 256k 36/512k Synchronous Sram
• Manufacturer: ETC-unknow

SAMPLE-Z
register, all output pins are forced to a High-Z state and the
boundary scan register is connected between TDI and TDO
pins when the TAP controller is in a Shift-DR state.
SAMPLE/PRELOA D
instruction. The PRELOAD portion of the command is not
implemented in this device, so the device TAP controller is
not fully IEEE 1149.1-compliant.
the instruction register and the TAP controller is in the
Capture-DR state, a snap shot of the data in the device’s input
and I/O buffers is loaded into the boundary scan register.
Because the device system clock(s) are independent from the
TAP clock (TCK), it is possible for the TAP to attempt to
capture the input and I/O ring contents while the buffers are in
transition (i.e., in a metastable state). Although allowing the
TAP to sample metastable inputs will not harm the device,
repeatable results can not be expected. To guarantee that the
boundary scan register will capture the correct value of a
signal, the device input signals must be stabilized long enough
to meet the TAP controller’s capture setup plus hold time (tCS
plus tCH). The device clock input(s) need not be paused for
any other TAP operation except capturing the input and I/O
ring contents into the boundary scan register.
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the
Update-DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
Pause-DR command.
BYPASS
instruction register and the TAP controller is in the Shift-DR
state, the bypass register is placed between TDI and TDO.
This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
RESERVED
use.
May 18, 199 9
Rev. 5/99
GALVANTECH
If the High-Z instruction is loaded in the instruction
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory
When the SAMPLE/PRELOAD instruction is loaded in
Moving the controller to Shift-DR state then places the
When the BYPASS instruction is loaded in the
Do not use these instructions. They are reserved for future
, INC.
256K X 36/512K X 18 SYNCHRONOUS SRAM
17
TDI
TDI
TDI
1
0
TAP CONTROLLER BLOCK DIAGRAM
TAP CONTROLLER STATE DIAGRAM
TEST-LOGIC
REUN-TEST/
Note: The 0/1 next to each state represents the value of
RESET
IDLE
0
Selection
Circuitry
TMS at the rising edge of TCK.
1
TAP CONTROLLER
GVT71256D36/GVT71512D18
Galvantech, Inc. reserves the right to change products or specifications without notice
*X = 69 for the x36 configuration;
*X = 50 for the x18 configuration.
31 30 29
x
Boundary Scan Register*
Boundary Scan Register*
Identification Register
.
1
0
Instruction Register
Bypass Register
Figure 3
Figure 4
.
CAPTURE-DR
1
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
SELECT
.
.
0
0
1
0
1
1
.
.
0
.
.
2
2
2
0
0
1
1
1
1
1
0
0
0
0
1
0
Selection
Circuitry
CAPTURE-IR
1
UPDATE-IR
PAUSE-IR
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
0
0
1
1
TDO
.