gvt71256d36 ETC-unknow, gvt71256d36 Datasheet

gvt71256d36

Manufacturer Part Number

gvt71256d36

Description

256k 36/512k Synchronous Sram

Manufacturer

ETC-unknow

Datasheet

1.GVT71256D36.pdf (25 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

gvt71256d36TA-6

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Current page: 1 of 25
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FEATURES

• Fast access times: 2.5ns, 3.0ns, and 3.5ns

• Fast clock speed: 225, 200, 166, and 150MHz

• Fast OE# access times: 2.5ns, 3.0ns, and 3.5ns

• Optimal for depth expansion (one cycle chip deselect to

• 3.3V -5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/O’s

• Clamp diodes to VSS at all inputs and outputs

• Common data inputs and data outputs

• BYTE WRITE ENABLE and GLOBAL WRITE control

• Multiple chip enables for depth expansion:

• Address pipeline capability

• Address, data and control registers

• Internally self-timed WRITE CYCLE

• Burst control pins (interleaved or linear burst sequence)

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119 bump, 14mm x 22mm PBGA (Ball Grid

OPTIONS

• Clock Cycle Timing

• Configurations

• Package Versions

GENERAL DESCRIPTIO N

employs high-speed, low power CMOS designs using

advanced

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688

Rev. 5/99

GALVANTECH

BURST SRAM

PIPELINED OUTPUT

SYNCHRONOUS

eliminate bus contention)

three chip enables for TA package version and two chip

enables for B and T package versions

Array) and 100 pin TQFP packages

4.4ns (225MHz)

5.0ns (200MHz)

6.0ns (166MHz)

6.7ns (150MHz)

256K x 36

512K x 18

119-bump PBGA

100-pin TQFP

The Galvantech Synchronous Burst SRAM family

triple-layer

Fax (408) 566-0699 Web Site http://www.galvantech.com

polysilicon,

MARKING

-4.4

-5

-6

-6.7

GVT71256D36

GVT71512D18

double-layer

, INC.

metal

256K X 36/512K X 18 SYNCHRONOUS SRAM

technology. Each memory cell consists of four transistors and

two high valued resistors.

integrate 262,144x36 and 524,288x18 SRAM cells with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated

by registers controlled by a positive-edge-triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE#), depth-

expansion chip enables (CE2 and CE2#), burst control inputs

(ADSC#, ADSP#, and ADV#), write enables (BWa#, BWb#,

BWc#, BWd#, and BWE#), and global write (GW#).

However, the CE2# chip enable input is only available for TA

package version.

and burst mode control (MODE). The data outputs (Q),

enabled by OE#, are also asynchronous.

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one to four bytes wide as controlled by the write control

inputs. Individual byte write allows individual byte to be

written. BWa# controls DQa. BWb# controls DQb. BWc#

controls DQc. BWd# controls DQd. BWa#, BWb# BWc#, and

BWd# can be active only with BWE# being LOW. GW#

being LOW causes all bytes to be written. The x18 version

only has 18 data inputs/outputs (DQa and DQb) along with

BWa# and BWb# (no BWc#, BWd#, DQc, and DQd).

implement JTAG test capabilities: test mode select (TMS),

test data-in (TDI), test clock (TCK), and test data-out (TDO).

The JTAG circuitry is used to serially shift data to and from

the device. JTAG inputs use LVTTL/LVCMOS levels to shift

data during this testing mode of operation. The TA package

version does not offer the JTAG capability.

The GVT71256D36 and GVT71512D18 operate from a

+3.3V power supply. All inputs and outputs are LVTTL

compatible

The

Asynchronous inputs include the output enable (OE#)

Addresses and chip enables are registered with either

Address, data inputs, and write controls are registered on-

For the B and T package versions, four pins are used to

256K x 36 SRAM

512K x 18 SRAM

+3.3V SUPPLY, FULLY REGISTERED

GVT71256D36

GVT71256D36/GVT71512D18

and

GVT71512D18

Galvantech, Inc. reserves the right to change

products or specifications without notice .

SRAMs

Related parts for gvt71256d36

gvt71256d36 Summary of contents

Page 1

... The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The TA package version does not offer the JTAG capability. The GVT71256D36 and GVT71512D18 operate from a +3.3V power supply. All inputs and outputs are LVTTL compatible double-layer ...

Page 2

... X 18 FUNCTIONAL BLOCK DIAGRAM BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register 17 Address Register CLR Binary Counter & Logic 2 GVT71256D36/GVT71512D18 OUTPUT REGISTER DQa,DQb D Q DQc,DQd Q OUTPUT REGISTER DQa DQb Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 3

... DQa MODE VCC VCCQ TMS TDI TCK TDO NC TOP VIEW 119 LEAD BGA 3 GVT71256D36/GVT71512D18 100 ...

Page 4

... Core power Supply: +3.3V -5% and +10% VSS Ground Ground: GND. VCCQ I/O Supply Output Buffer Supply: +2.5V or +3.3V Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS. 4 GVT71256D36/GVT71512D18 DESCRIPTIO N Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 5

... VCCQ TMS TDI TCK TDO NC TOP VIEW 119 LEAD BGA 5 GVT71256D36/GVT71512D18 100 100-pin TQFP TA version VCCQ DQa VCCQ ...

Page 6

... Core power Supply: +3.3V -5% and +10% VSS Ground Ground: GND. VCCQ I/O Supply Output Buffer Supply: +2.5V or +3.3V Connect: These signals are not internally connected. User can leave it floating or connect it to VCC or VSS. 6 GVT71256D36/GVT71512D18 DESCRIPTIO N Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 7

... X 36/512K X 18 SYNCHRONOUS SRAM Third Address Fourth Address (internal ) (internal ) A...A10 A...A11 A...A11 A...A10 A...A00 A...A01 A...A01 A...A00 Third Address Fourth Address (internal ) (internal ) A...A10 A...A11 A...A11 A...A00 A...A00 A...A01 A...A01 A...A10 7 GVT71256D36/GVT71512D18 Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 8

... BWE# BWa# BWb# BWc GVT71256D36/GVT71512D18 ADV# WRITE# OE# CLK L-H High L-H High L-H High L-H High L-H High L L-H High-Z ...

Page 9

... VCCQ VCCQ SYM TYP or > Icc 150 SB2 SB3 I 40 SB4 ; VCC = MAX; IH CONDITION S SYMBO L TQFP TY P Still air, soldered on 4. 1.125 inch 4-layer GVT71256D36/GVT71512D18 MIN MAX UNITS NOTES 2.0 VCC+0.3 V 2.0 4.6 V -0 2.4 V 0.4 V 3.135 3 ...

Page 10

... VCCQ 2.5 3.0 =3.3V VCCQ 3.0 3.5 =2. 2.5 2.5 1.5 1.5 0.5 0.5 CONDITION S SYMBO MHz C I VCC = 3. OUTPUT LOW VOLTAG VOL (V) -105 -0.5 -105 0 -105 0.4 -83 0.8 -70 1.25 -30 1.6 -10 2.8 0 3.2 0 3.4 10 GVT71256D36/GVT71512D18 - 6 - 6.7 166MHz 150MHz MIN MAX MIN MAX UNITS 6.0 6.7 ns 2.4 2.6 ns 2.4 2.6 ns 3.5 3.5 ns 4.0 4.5 ns 1.25 1. 1.25 4.0 1.25 4.0 ns 3.5 3.5 ns 4.0 4 3.5 3.5 ns 1.8 2.0 ns 0.5 0.5 ns TYP ...

Page 11

... MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of + KQHZ is less 15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig Fig. 1A. 11 GVT71256D36/GVT71512D18 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v ...

Page 12

... For X18 product, there are only BWa# and BWb# for byte write control. May 18, 199 9 Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM READ TIMIN OEQ t OELZ Q(A1) Q(A2) Q(A2+1) SINGLE READ 12 GVT71256D36/GVT71512D18 Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 13

... For X18 product, there are only BWa# and BWb# for byte write control. May 18, 199 9 Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 13 GVT71256D36/GVT71512D18 D(A2+2) D(A2+3) D(A3) D(A3+1) BURST WRITE Galvantech, Inc. reserves the right to change products or specifications without notice D(A3+2) . ...

Page 14

... For X18 product, there are only BWa# and BWb# for byte write control. May 18, 199 9 Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM READ/WRITE TIMIN Q(A1) Q(A2) D(A3) Single Write 14 GVT71256D36/GVT71512D18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 15

... The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the 15 GVT71256D36/GVT71512D18 Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 16

... TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power- up and at any time the TAP controller is placed in the test- logic reset state. 16 GVT71256D36/GVT71512D18 (private) instructions. Some Galvantech, Inc. reserves the right to change products or specifications without notice public ...

Page 17

... RESET 0 REUN-TEST/ 0 IDLE Note: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. TAP CONTROLLER STATE DIAGRAM Selection TDI Circuitry TDI TDI TAP CONTROLLER BLOCK DIAGRAM 17 GVT71256D36/GVT71512D18 1 1 SELECT SELECT DR-SCAN IR-SCAN CAPTURE-DR CAPTURE- SHIFT-DR ...

Page 18

... VCC - -5 < VCCQ IN = 100uA V OLC = 100uA VCC - 0.2 V OHC = 8.0mA V OLT = 8.0mA V 2.4 OHT t KHKH/2. t KHKH/2 18 GVT71256D36/GVT71512D18 1.5V Figure 5 MAX UNITS NOTES VCC + 5 Galvantech, Inc. reserves the right to change products or specifications without notice ...

Page 19

... TLQX SYM MIN MAX UNITS t THTH MHz t THTL TLTH TLQX TLQV DVTH THDX MVTH THMX GVT71256D36/GVT71512D18 t TLTH Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 20

... Defines width of x36 or x18 bits. XXXXXX Reserved for future use. 00011100100 Allows unique identification of DEVICE vendor Indicates the presence register. BIT SIZE (x18 ) GVT71256D36/GVT71512D18 Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 21

... GVT71256D36/GVT71512D18 BWa BWb BWc BWd CE2 100 2A DQc 1 2D DQc 2 1E DQc 3 2F DQc ...

Page 22

... GVT71256D36/GVT71512D18 DQb 9 2E DQb 12 2G DQb DQb 18 2K DQb 19 1L DQb 22 2M DQb 23 1N DQb 24 2P MODE ...

Page 23

... GALVANTECH 100 Pin TQFP Package Dimension 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters May 18, 199 9 Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 23 GVT71256D36/GVT71512D18 0.30 + 0.08 0.60 + 0.15 Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 24

... Note: All dimensions in Millimeters May 18, 199 9 Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM 22.00 + 0.20 20.32 1. BOTTOM VIEW 19.50 + 0.10 TOP VIEW SIDE VIEW 24 GVT71256D36/GVT71512D18 0.60 + 0.10 Galvantech, Inc. reserves the right to change products or specifications without notice . ...

Page 25

... Rev. 5/99 , INC. 256K X 36/512K X 18 SYNCHRONOUS SRAM Speed ( 4.4 = 2.5ns access/4.4ns cycle Speed ( 4.4 = 2.5ns access/4.4ns cycle 25 GVT71256D36/GVT71512D18 5 = 2.5ns access/5.0ns cycle 6 = 3.5ns access/6.0ns cycle 6.7 = 3.5ns access/6.7ns cycle) Package (B = 119 BUMP PBGA 100 PIN TQFP, T Version) TA= 100 PIN TQFP, TA Version ...

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