m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 4

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

1.0 DDR3 Unbuffered SoDIMM Ordering Information
* ## : F8 / H9
** F8 : 1066Mbps 7-7-7, H9 : 1333Mbps 9-9-9
2.0 Key Features
3.0 Address Configuration
Unbuffered SoDIMM
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
• 533MHz f
• 8 independent internal bank
• Programmable CAS Latency: 6,7,8,9
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 6(DDR3-1066), 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
• Asynchronous Reset
write [either On the fly using A12 or MRS]
CAS Latency
tRCD(min)
tRAS(min)
DDQ
tCK(min)
tRP(min)
tRC(min)
Speed
256x8(2Gb) based Module
M471B5273BH1-CF8/H9
= 1.5V ± 0.075V
Part Number
CK
Organization
for 1066Mb/sec/pin, 667MHz f
DDR3-1066
13.125
13.125
50.625
1.875
7-7-7
37.5
Density
7
CK
4GB
Row Address
CASE
for 1333Mb/sec/pin
A0-A14
85
°
C, 3.9us at 85
Organization
512Mx64
4 of 28
°
Column Address
C < T
CASE
A0-A9
256Mx8(K4B1G0846B-HC##)*16
Component Composition
< 95
DDR3-1333
°
C
9-9-9
13.5
13.5
49.5
1.5
36
9
Bank Address
BA0-BA2
Rev. 1.0 December 2008
DDR3 SDRAM
Number of
Rank
Auto Precharge
2
Unit
tCK
ns
ns
ns
ns
ns
A10/AP
Height
30mm