m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 13

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Notes:
1. For CK, CK use V
2. V
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
ended components of differential signals the requirement to reach V
10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach V
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach V
preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
mode charateristics of these signals.
Unbuffered SoDIMM
signal group, then the reduced level applies also here
limits (V
Specification"
IH
Symbol
(AC)/V
V
V
SEH
SEL
IH
(DC) max, V
IL
(AC) for DQs is based on V
DD
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
IH
/V
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
IL
IL
V
(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
DD
V
/2 or V
V
DD
SS
V
V
SEL
or V
SEH
or V
Parameter
DDQ
max
DDQ
SSQ
min
/2
REFDQ
SEH
Figure 4 : Single-ended requirement for differential signals.
min / V
; V
SEH
IH
(AC)/V
SEL
min / V
max (approximately equal to the ac-levels ( V
IL
(AC) for ADD/CMD is based on V
SEL
max (approximately the ac-levels ( V
13 of 28
SEL
V
max, V
SEH
(V
(V
DD
DD
Note3
Note3
REF
/2)+0.175
/2)+0.175
Min
SEH
, the single-ended components of differential signals have a requirement
min has no bearing on timing, but adds a restriction on the common
DDR3-1066/1333
REFCA
; if a reduced ac-high or ac-low level is used for a
IH
IH
(AC) / V
IH
V
(AC) / V
150(AC)/V
SEL
IH
Rev. 1.0 December 2008
(V
(V
/V
IL
DD
DD
IL
(AC) of DQs.
IL
(AC) ) for DQ signals) in every half-cycle
Note3
Note3
Max
/2)-0.175
/2)-0.175
(AC) ) for ADD/CMD signals) in every
CK or DQS
IL
150(AC) is used for ADD/CMD sig-
DDR3 SDRAM
time
Unit
V
V
V
V
Notes
1, 2
1, 2
1, 2
1, 2