mt18hvs25672rhy-667 Micron Semiconductor Products, mt18hvs25672rhy-667 Datasheet - Page 8

• Manufacturer Part Number: mt18hvs25672rhy-667
• Description: 2gb X72, Dr 200-pin Ddr2 Sdram Vlp Sordimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef82882ad5/Source: 09005aef82882b0e
HVS18C_256x72RH.fm - Rev. B 5/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open:
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open, continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open, continuous burst
reads; I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switching.
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RCD =
CK =
RAS =
RP =
RAS =
CK =
Specifications
t
t
t
t
RP (I
RC (I
CK (I
CK (I
t
t
t
OUT
OUT
RCD (I
RAS MAX (I
RAS MAX (I
DD
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address
),
DDR2 I
Values shown for MT47H256M8THN DDR2 SDRAM only and are computed from values specified in the
2Gb TwinDie
DD
); CKE is LOW; Other control and address bus
),
t
t
RAS =
); CKE is HIGH, S# is HIGH between valid commands; Address
RC =
DD
DD
t
t
),
),
CK =
DD
RC (I
t
RAS MIN (I
t
t
DD
RP =
RP =
t
CK =
Specifications and Conditions – 2GB
), AL = 0;
TM
DD
t
CK (I
t
t
),
(256 Meg x 8) component data sheet.
RP (I
RP (I
t
CK (I
t
RRD =
DD
DD
DD
DD
),
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
t
RC =
); Refresh command at every
), AL = 0;
), AL =
t
RRD (I
t
CK (I
t
RC (I
t
DD
RCD (I
DD
t
),
DD
CK =
),
t
t
DD
RCD =
),
CK =
t
t
2GB (x72, DR) 200-Pin DDR2 SDRAM VLP SORDIMM
DD
RAS =
t
CK =
t
4W
RAS =
CK =
t
CK (I
) - 1 ×
t
CK (I
t
t
OUT
t
RCD (I
CK (I
CK =
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
8
t
DD
),
CK (I
= 0mA; BL = 4,
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
t
),
DD
DD
CK (I
t
),
CK (I
DD
); CKE is
); CKE is
t
RFC (I
);
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
DD
);
DD
);
),
),
)
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
1,008
1,278
1,323
2,043
2,638
-667
873
126
603
468
270
603
126
90
©2007 Micron Technology, Inc. All rights reserved.
I
1,188
1,233
1,998
2,538
DD
-53E
738
963
126
612
468
270
513
126
90
Specifications
1,008
1,053
1,953
2,448
-40E
738
918
126
621
423
270
468
126
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA