mt18hvs25672rhy-667 Micron Semiconductor Products, mt18hvs25672rhy-667 Datasheet - Page 16

• Manufacturer Part Number: mt18hvs25672rhy-667
• Description: 2gb X72, Dr 200-pin Ddr2 Sdram Vlp Sordimm
• Manufacturer: Micron Semiconductor Products

Temperature Format
Upper Temperature Boundary Register
Table 22:
Lower Temperature Boundary Register
Table 23:
Critical Temperature Register
Table 24:
PDF: 09005aef82882ad5/Source: 09005aef82882b0e
HVS18C_256x72RH.fm - Rev. B 5/08 EN
15
15
15
0
0
0
14
14
14
0
0
0
Upper Temperature Boundary Register Bits
Lower Temperature Boundary Register Bits
Critical Temperature Register Bits
13
13
13
0
0
0
MSB
MSB
MSB
12
12
12
The temperature trip point registers and temperature readout register use a
“2’s complement” format to enable negative numbers. The least significant bit is equal
to 0.0625°C or 0.25°C depending on which register is referenced. As an example,
assuming a LSB of 0.0625°C:
• A value of 0x018C would equal 24.75°C
• A value of 0x06C0 would equal 108°C
• A value of 0x1E74 would equal –24.75°C
The upper temperature boundary register is used to set the maximum value of the alarm
window. The least significant bit for this register is 0.25°C. All RFU bits in the register will
always report zero.
The lower temperature boundary register is used to set the minimum value of the alarm
window. The least significant bit for this register is 0.25
always report zero.
The critical temperature register is used to set the maximum temperature above the
alarm window. The least significant bit for this register is 0.25°C. All RFU bits in the
register will always report zero.
11
11
11
10
10
10
Alarm window upper boundary temperature
Alarm window lower boundary temperature
9
9
9
Critical temperature trip point
2GB (x72, DR) 200-Pin DDR2 SDRAM VLP SORDIMM
8
8
8
16
7
7
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
6
6
5
5
5
o
4
C. All RFU bits in the register will
4
4
Temperature Sensor
©2007 Micron Technology, Inc. All rights reserved.
3
3
3
LSB
LSB
LSB
2
2
2
RFU
RFU
RFU
1
1
1
RFU
RFU
RFU
0
0
0