zl50235 Zarlink Semiconductor, zl50235 Datasheet - Page 35

• Manufacturer Part Number: zl50235
• Description: 16 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Bit 7
Unused
Unused
Format
MTDBI
MTDAI
PWUP
Unused
Unused
Law
I<4:0>
Bit 7
IRQ
IRQ
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
Bit 6
Unused
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code
A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded
PCM code
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register
is read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit.
Unused bit.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Unused
.
Bit 6
Power-up 00
Main Control Register 1 (EC Group 1)
Main Control Register 2 (EC Group 2)
Main Control Register 3 (EC Group 3)
Main Control Register 4 (EC Group 4)
Main Control Register 5 (EC Group 5)
Main Control Register 6 (EC Group 6)
Main Control Register 7 (EC Group 7)
.
hex
Bit 5
Unused
to Base Address+3F
Unused
Bit 5
Power-up 00
hex
Functional Description of Register Bits
Functional Description of Register Bits
Bit 4
MTDBI
Interrupt FIFO Register
Zarlink Semiconductor Inc.
Bit 4
hex
I4
hex
ZL50235
, to default Reset Value and clears the Adaptive Filter
35
Bit 3
MTDAI
Bit 3
I3
Bit 2
Format
R/W Address: 410
Bit 2
I2
Bit 1
Law
R/W Address: 401
R/W Address: 402
R/W Address: 403
R/W Address: 404
R/W Address: 405
R/W Address: 406
R/W Address: 407
Bit 1
I1
hex
Data Sheet
Bit 0
PWUP
Bit 0
I0
hex
hex
hex
hex
hex
hex
hex