zl50235 Zarlink Semiconductor, zl50235 Datasheet - Page 13

• Manufacturer Part Number: zl50235
• Description: 16 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

The NLPSel bit in Control Register 3 selects which NLP is used. A “1” will select the Advanced NLP, “0” selects the
original NLP. (See page 29 - Control Register 3 bit description)
The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background
noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3
selects the ramping scheme.
The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the
Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher
value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.
The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will
scale the injected noise level down, conversely, raising the value will scale the comfort noise up. Due to differences
in the noise estimator operation, the Advanced NLP requires a different scaling value than the original NLP.
IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant
values. Changing these values may result in undesirable comfort noise performance!
The Advanced NLP also contains safeguards to prevent double-talk and uncanceled echo from being mistaken for
background noise. These features were not present in the original NLP. They can be disabled by setting the
NLRun1 and NLRun2 bits in Control Register 3 to “0”.
2.5
The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21 Hz) sine
wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every
450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the
Tone Detector will trigger.
The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between
0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone
Detector will trigger.
The ZL50235 has two Tone Detectors per channels (for a total of 32) in order to monitor the occurrence of a valid
disable tone on both Rin and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic
high and an interrupt is generated (i.e., IRQ pin low). Refer to Figure 5 and to the Interrupts section.
Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to
maintain Tone Detector status (i.e., TD bit high). The Tone Detector status will only release (i.e., TD bit low) if the
signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the
frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is
generated (i.e., IRQ pin low).
Disable Tone Detector
Rin
Sin
Rin
Sin
Figure 5 - Disable Tone Detection
Tone
Tone
Tone
Tone
Zarlink Semiconductor Inc.
Echo Canceller A
Echo Canceller B
Detector
Detector
Detector
Detector
ZL50235
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Status reg
Status reg
TD
TD bit
ECA
ECB
bit
Data Sheet