zl50235 Zarlink Semiconductor, zl50235 Datasheet - Page 20

• Manufacturer Part Number: zl50235
• Description: 16 Channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

7.4
On power up, the RESET pin must be held low for 100 µs. Forcing the RESET pin low will put the ZL50235 in
power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated.
The 8 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero.
When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to
lock. C4i and F0i can be active during this period. At this point, the echo canceller must have the internal registers
reset to an initial state. This is accomplished by one of two methods. The user can either issue a second hardware
reset or perform a software reset. A second hardware reset is performed by driving the RESET pin low for at least
500 ns and no more than 1500 ns before being released. A software reset is accomplished by programming a “1” to
each of the PWUP bits in the Main Control Registers, waiting 250 µs (2 frames) and then programming a “0” to
each of the PWUP bits.
The user must then wait 500 µs for the PLL to relock. Once the PLL has locked, the user can power up the 16
groups of echo cancellers individually by writing a “1” into the PWUP bit in Main Control Register of each echo
canceller group.
For each group of echo cancellers, when the PWUP bit toggles from zero to one, echo cancellers A and B execute
their initialization routine. The initialization routine sets their registers, Base Address+00
to the default Reset Value and clears the Adaptive Filter coefficients. Two frames are necessary for the initialization
routine to execute properly.
Once the initialization routine is executed, the user can set the per channel Control Registers, Base Address+00
to Base Address+3F
Power Up Sequence
hex
, for the specific application.
Group 0
Echo
Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Groups 2 --> 6
Echo Cancellers
Registers
Group 7
Echo
Cancellers
Registers
Channel 0, ECA Ctrl/Stat Registers
Channel 1, ECB Ctrl/Stat Registers
Channel 2, ECA Ctrl/Stat Registers
Channel 3, ECB Ctrl/Stat Registers
Channel 14, ECA Ctrl/Stat Registers
Channel 15, ECB Ctrl/Stat Registers
Main Control Registers <7:0>
Interrupt FIFO Register
Test Register
Reserved Test Register
Figure 10 - Memory Mapping
Zarlink Semiconductor Inc.
ZL50235
20
0000h -->
0020h -->
0040h -->
0060h -->
01C0h -->
01E0h -->
0400h --> 0407h
0410h
0411h
0412h ---> FFFFh
001Fh
003Fh
005Fh
007Fh
01DFh
01FFh
hex
to Base Address+3F
Data Sheet
hex
hex
,