zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 7

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

1.3.5
The output of the DCO is connected to the Clock Synthesizer that generates the output clocks and frame pulse.
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In addition to the above, LK1 also generates a 19.44 MHz clock, which is linked externally to LK2. This clock drives
the APLL stage which generates the low jitter 19.44 MHz and 155.52 MHz clock outputs (see Section 1.4).
1.3.6
The ZL30462 is considered locked (LOCK=1) when the residual phase movement after declaring locked condition
does not exceed 20 ns; as required by standard wander generation MTIE and TDEV tests. To ensure the integrity of
the LOCK status indication, the ZL30462 holds the LOCK pin low for a minimum of 10 sec.
1.4
The ZL30462 output driver circuit provides two LVPECL jitter attenuated outputs at 155.52 MHz and one CMOS
output at 19.44 MHz.
There are no external components or adjustments required to support this part of the circuit, as the loop filter and
additional power supply decoupling circuitry has been built into the module.
The on-board loop filter has been optimized to ensure the quality of the jitter attenuated output. But to maintain the
quality of these outputs it is extremely important that they are terminated correctly and the track impedance is
50 Ohms. Failure to do so will affect the modules performance will affect the quality of these clocks. Figure 3 shows
one method of terminating one of the LVPECL outputs, further termination information can be found in the ZL30462
Applications Note.
The input to the APLL stage can be isolated from the DPLL, by removing the link connection between LK1 (pin 5)
and LK2 (pin 6), this may be useful for product verification or test purposes.
C2o: 2.048 MHz clock with nominal 50% duty cycle
C8o: 8.192 MHz clock with nominal 50% duty cycle
C16o: 16.384 MHz clock with nominal 50% duty cycle
F16o: 8 kHz frequency, with 61 ns wide, logic low frame pulse
Jitter Attenuator
LK1:
Clock Synthesizer
Lock Indicator (LOCK)
19.44 MHz clock with nominal 50% duty cycle
Zarlink Semiconductor Inc.
ZL30462
6
Data Sheet