zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 4

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

Pin Description Table (continued)
Pin Number
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
HOLDOVER HOLDOVER (CMOS Output). This output goes to a logic high whenever the PLL
JA155N-1
JA155P-1
AGND2
AGND1
AGND1
RESET
TGND
Name
TCLR
RSEL
TV
V
V
OSC
SEC
MS1
MS2
PRI
NC
NC
NC
NC
IC
IC
DD3
DD1
DD
JA 155-1 Clock (LVPECL Output). This differential output provides a low jitter
155.52 MHz clock.
Ground.
Positive Power Supply.3.3 V
Ground.
Oscillator Positive Power Supply. 3.3 V
Oscillator Ground.
Oscillator Master Clock (CMOS Output). This pin can be used to monitor the
output of the on-board master oscillator.
Positive Power Supply. 3.3 V
Primary Reference (Input). This input is a Primary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 0 is applied to the RSel input pin. This pin is
internally pulled up to V
Secondary Reference (Input). This input is a Secondary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 1 is applied to the RSel input pin. This pin is
internally pulled up to V
Internal Connection. Do not connect to this pin.
TIE Circuit Reset (Input). A high to low transition at this input initiates phase
realignment between the input reference and the generated output clocks. This
pin is internally pulled to GND.
Reset (Input). Logic 0 will forces the module into a reset state. This pin must be
held to logic 0 for a minimum of 1µs to reset the module properly. The module
must be reset after power-up.
Ground.
Internal Connection. Do not connect to this pin.
No Connection. This pin is unused and has no internal connection.
No Connection. This pin is unused and has no internal connection.
Reference Source Select (Input). A logic low selects the PRI (primary) reference
source as the input reference signal and a logic high selects the SEC (secondary)
input. This pin is internally pulled down to GND. See Table 1.
Mode/Control Select 1 (Input). This input, in conjunction with MS2, determines
the state (Normal, Holdover or Freerun) of operation. See Table 2.
Mode/Control Select 2 (Input). This input, in conjunction with MS1, determines
the state (Normal, Holdover or Freerun) of operation. See Table 2.
No Connection. This pin is unused and has no internal connection.
goes into holdover mode.
No Connection. This pin is unused and has no internal connection.
Zarlink Semiconductor Inc.
ZL30462
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DD
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Description
Data Sheet