zl30462 Zarlink Semiconductor, zl30462 Datasheet
zl30462
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zl30462 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30462MCF 40 SMTDIL Description The ZL30462 is a Timing Module, which functions as a complete system clock solution for general timing applications. The ZL30462 has been designed around Zarlink's ...
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... LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the input reference. 15 JA19Mo Clock 19.44 MHz (CMOS Output). This output provides a low jitter 19.44 MHz clock. ZL30462 Figure Pin SMT DIL Top View Description 2 Zarlink Semiconductor Inc. ...
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... NC No Connection. This pin is unused and has no internal connection. 38 HOLDOVER HOLDOVER (CMOS Output). This output goes to a logic high whenever the PLL goes into holdover mode Connection. This pin is unused and has no internal connection. ZL30462 Description . Zarlink Semiconductor Inc. ...
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... PLL reference by using the TCLR control pin. Using TCLR If the ZL30462 is locked to a reference, then the output clocks can be brought into phase alignment with the PLL reference by using the TCLR control pin according to the procedure below: • ...
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... Loop Filter In Normal mode, the clocks generated by the ZL30462 are phase-locked to the input reference signal. The DPLL Loop Filter is similar to a first order low pass filter with a 1.5 Hz cutoff frequency for all four reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the wander transfer requirements in ETS 300 011 and AT& ...
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... Ohms. Failure will affect the modules performance will affect the quality of these clocks. Figure 3 shows one method of terminating one of the LVPECL outputs, further termination information can be found in the ZL30462 Applications Note. ...
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... DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the ZL30462 is based on the incoming signal 30 ms minimum prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., <±0.01 ppm, relative to the master oscillator frequency) ...
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... Free-run state (MS2, MS1 = 10 recommended that a module reset is performed immediately after power up, to ensure the ZL30462 is set to a know state. The RESET function would normally be under the control of the system or host controller, usually in the form of a microprocessor or FPGA ...
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... Auto Holdover until that input becomes valid. This is an internal protection system, to ensure that the module does not use an invalid reference. If the ZL30462 is reset at any time (e.g., during power-up) and mode select pins are trying to force the module to lock to an invalid input (MS1, MS2 == 00) the module will transition into Auto Holdover and the HOLDOVER pin will be asserted. Because the reset function clears the ZL30462’ ...
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... DPLL to move into and out of the Auto Holdover state. The ZL30462 State Machine may also be driven by controlling the mode select pins MS2, MS1. To avoid network synchronization problems, the State Machine has built-in basic protection that does not allow switching the DPLL into a state where it cannot operate correctly e.g not possible to force the DPLL into Normal mode when all references are lost ...
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... The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure time when ZL30462 operates in Normal mode. This failure is detected at the active input based on the following FAIL criteria: • ...
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... So, changing the input reference under controlled conditions should avoid any unnecessary chances of generating a phase hit. ______ RESET == 1 MS2, MS1 != 10 FreeRun Reset MS2, MS1 == 10 forces unconditional return from any state to FreeRun ZL30462 MS2, MS1 == 01 or RSEL change Normal (Locked) 00 Ref: OK & MS2, MS1 == 00 {Auto} Holdover ...
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... Semi-automatic transition, which involves changing the RSEL input to select the other reference clock, without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces ZL30462 to momentarily transition through the Holdover state and automatically return to Normal state after synchronizing to the other reference clock. ...
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... LVPECL: High-level output voltage 10 LVPECL: Low-level output voltage 11 LVPECL: Output rise and fall times * Voltages are with respect to ground (GND) unless otherwise stated. Note 1: Rise and fall times are measured at 20% and 80% levels. ZL30462 Symbol Symbol Min ...
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... AC Electrical Characteristics* - Timing Parameter Measurements - CMOS Voltage Levels* 1 Threshold voltage 2 Rise and fall threshold voltage High 3 Rise and fall threshold voltage Low * Voltages are with respect to ground (GND) unless otherwise stated. All Signals T IF Figure 11 - Timing Parameters Measurement Voltage Levels ZL30462 Symbol Min -0. -104 ...
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... MHz ref. input to F16o delay 9 Reference input rise and fall time PRI/SEC 8kHz tc = 125µs PRI/SEC 1.544MHz tc = 647.67ns PRI/SEC 2.048MHz tc = 488.28ns PRI/SEC 19.44MHz tc = 51.44ns /F16o tc = 125µs Figure 12 - Input to Output Timing (Normal Mode) ZL30462 Symbol Min. Max. t 100 R8H R8D t 100 R1.5H t 360 393 R1.5D ...
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... Input Controls Hold Time /F16o MS1, MS2, RSEL, Figure 13 - Input Control Signal Setup and Hold Time AC Electrical Characteristics - Outputs Timing Characteristics 1 F16o to JA19Mo delay 4 F16o to C16o delay 5 F16o to C8o delay 6 F16o to C2o delay ZL30462 Symbol Min. t 100 S t 100 Symbol Min. ...
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... JA19Mo tc = 51.44ns /C16o tc = 61.035ns C8o tc = 122.07ns C2o tc = 488.28ns Figure 14 - Output Timing ZL30462 t J19D t C16D t C8D t C2D 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Equivalent Limit in limit in TYP UI time domain C16o, C8 and C2 Clock Outputs 0.05 UI 24.4 1. Zarlink Semiconductor Inc. Data Sheet ZL30462 Jitter Generation Performance TYP Units Notes JA155P/N Clock Output 24.2 ps P-P ps RMS JA19Mo Clock Output ps P-P ps RMS ps P-P ps RMS ZL30462 Jitter Generation Performance Units Notes ns P-P ...
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... Performance Characteristics: Measured Output Jitter - G.813 conformance - Option 2 ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-4 12 kHz to 5 MHz 622.08 Mbit/s 2 STM-1 65 kHz to 1.3 MHz 155.54 Mbit/s ZL30462 ZL30462 Jitter Generation Performance Equivalent Limit in limit in TYP UI time domain 0.1 UI 161 11.9 PP 0.94 0.1 UI 643 283 ...
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... Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE --- ACN 15 Oct 03 DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...