zl30462 Zarlink Semiconductor, zl30462 Datasheet - Page 5

• Manufacturer Part Number: zl30462
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Zarlink Semiconductor

Pin Description Table (continued)
1.0
The ZL30462 offers a complete timing solution in a 1.2” x 1” module package. The module comprises three main
components, a DPLL which performs the main operational functions, an APLL which provides three low jitter output
clocks and an on-board master oscillator. Figure 1 shows a functional block diagram of the module, which is
described in the following sections.
1.1
The ZL30462 accepts two simultaneous reference input signals which can be derived from independent sources.
Both reference inputs will automatically accept one of four frequencies, 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz. The 8 kHz, 1.544 MHz and 2.048 MHz input clocks are all triggered on the falling edge and the
19.44 MHz is triggered on the rising edge. The primary reference (PRI) signal or the secondary reference (SEC)
signal can be selected by simply using the RSEL pin, see Table 1.
1.2
When the ZL30462 finishes locking to a reference an arbitrary phase difference will remain between its output
clocks and its reference; this phase difference is part of the normal operation of the ZL30462. If so desired, the
output clocks can be brought into phase alignment with the PLL reference by using the TCLR control pin.
Using TCLR
If the ZL30462 is locked to a reference, then the output clocks can be brought into phase alignment with the PLL
reference by using the TCLR control pin according to the procedure below:
•
•
•
•
This sequence re-initiates the ZL30462 locking procedure; the LOCK indicator will go low 5 sec after TCLR is pulled
low and will remain low for 10 sec.
1.3
The most critical element of the ZL30462 is the Core PLL. This generates a phase-locked clock filters wander and
suppresses input phase transients.The Core PLL supports three mandatory modes of operation: Free-run, Normal
(Locked) and Holdover.
Each of these modes places specific requirements on the building blocks of the Core PLL.
Pin Number
Wait until the ZL30462 LOCK indicator is high, indicating that it is locked
Pull TCLR low
Hold TCLR low for 250 µs for 1.544 MHz, 2.048 MHz or 19.44 MHz, or 10 sec for 8 kHz (input frequency).
Pull TCLR high
RSEL
40
Time Interval Error (TIE) Corrector Circuit
Reference Select MUX Circuit
Core PLL
Functional Description
0
1
PRI
SEC
Name
V
DD
Positive Power Supply. 3.3 V
Table 1 - Input Reference Selection
Zarlink Semiconductor Inc.
ZL30462
Input Reference
4
Description
Data Sheet