ht82a821r Holtek Semiconductor Inc., ht82a821r Datasheet - Page 10

• Manufacturer Part Number: ht82a821r
• Description: Ht82a821r -- Usb Audio Mcu
• Manufacturer: Holtek Semiconductor Inc.

Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSCI and OSCO is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. Instead of a
crystal, a resonator can also be connected between
OSCI and OSCO to get a frequency reference, but two
external capacitors in OSCI and OSCO are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works. The
WDT oscillator can be disabled by ROM code option to
conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or a instruction clock (sys-
tem clock/4). The timer is designed to prevent a soft-
ware malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by options. But if the WDT is disabled,
all executions related to the WDT lead to no operation.
When the WDT clock source is selected, it will be first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
Rev. 1.10
Bit No.
7~4
0
1
2
3
T3~T0
Label
WS0
WS1
WS2
System Oscillator
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, division ratio = 1:1
Bit 2,1,0 = 001, division ratio = 1:2
Bit 2,1,0 = 010, division ratio = 1:4
Bit 2,1,0 = 011, division ratio = 1:8
Bit 2,1,0 = 100, division ratio = 1:16
Bit 2,1,0 = 101, division ratio = 1:32
Bit 2,1,0 = 110, division ratio = 1:64
Bit 2,1,0 = 111, division ratio = 1:128
Unused bit, read as 0
Test mode setting bits
(T3, T2, T1, T0)=(0, 1, 0, 1), enter DAC write mode. Otherwise normal operation.
WDTS (09H) Register
10
The WDT OSC period is typical 65 s. This time-out pe-
riod may vary with temperature, VDD and process varia-
tions. The WDT OSC always works for any operation
mode.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the halt mode. In the mode, the WDT stops counting and
lose its protecting purpose. In this situation the logic can
only be re-started by external logic. The high nibble and
bit3 of the WDTS are reserved for user defined flags,
which can be used to indicate some specified status.
The WDT overflow under normal operation initializes a
mode, the overflow initializes a warm reset , and only
the PC and SP are reset to zero. To clear the contents of
the WDT, there are three methods to be adopted, i.e.,
external reset (a low level to RESET), software instruc-
tion, and a HALT instruction. There are two types of
software instructions; CLR WDT and the other set
instruction, only one type of instruction can be active at a
time depending on the options CLR WDT times selec-
tion option. If the CLR WDT is selected (i.e., CLR WDT
times equal one), any execution of the CLR WDT in-
struction clears the WDT. In the case that CLR WDT1
and CLR WDT2 are chosen (i.e., CLR WDT times
equal two), these two instructions have to be executed
to clear the WDT; otherwise, the WDT may reset the
chip due to time-out.
chip reset and sets the status bit TO . In the HALT
CLR WDT1 and CLR WDT2 . Of these two types of
Function
Watchdog Timer
HT82A821R
June 29, 2007