ht82a821r Holtek Semiconductor Inc., ht82a821r Datasheet
ht82a821r
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ht82a821r Summary of contents
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... The gain range is from 32dB to +6dB. The HT82A821R has a Human Interface Device func- tion that allows a user to control the playback volume at the device side. The HT82A821R also can mute the an- alog output signal by the operation of HID buttons. 1 June 29, 2007 ...
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... Block Diagram Pin Assignment Rev. 1.10 2 HT82A821R June 29, 2007 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.10 Description +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH 3 HT82A821R June 29, 2007 ...
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... Line output series capacitor with 220 load 5V 8 load 4 load 5V 8 load 4 load 5V 8 load 4 load, THD=10 load, THD=10% Test Conditions Min. V Conditions HT82A821R Ta=25 C Typ. Max. Unit 5 5 146 ...
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... Program Counter Program Counter S10~S0: Stack register bits @7~@0: PCL bits 5 HT82A821R * ...
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... At the end of a subroutine or an interrupt routine, Table Location * Table Location P10~P8: Current program counter bits when TBHP is disabled TBHP register bit2~bit0 when TBHP is enabled 6 HT82A821R * June 29, 2007 ...
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... Except for some dedicated bits, each bit in the Rev. 1. RAM Mapping data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0 or MP1). 7 HT82A821R June 29, 2007 ...
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... Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only Function Status (0AH) Register 8 HT82A821R June 29, 2007 ...
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... HT82A821R is set and a USB interrupt is also triggered. When the HT82A821R receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82A821R are set and a USB interrupt is triggered. Also when HT82A821R receive a Resume signal from Host PC, the resume line (bit3 of USC) of HT82A821R is Bit No. Label 0 EMI Controls the master (global) interrupt (1=enable ...
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... WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e., CLR WDT times equal two), these two instructions have to be executed to clear the WDT; otherwise, the WDT may reset the chip due to time-out. Watchdog Timer Function WDTS (09H) Register 10 HT82A821R June 29, 2007 ...
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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. (system clock Reset Timing Chart Reset Configuration 11 HT82A821R RESET Conditions Reset Circuit June 29, 2007 ...
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... HT82A821R USB-Reset USB-Reset (Normal) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H 000H ...
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... In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an in- terrupt request the other two modes, i.e., event and timer modes. Function TMRC (11H) Register Timer/Event Counter 0/1 13 HT82A821R June 29, 2007 ...
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... Each line of port A has the capability of waking-up the device recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. Input/Output Ports 14 HT82A821R June 29, 2007 ...
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... Also the user can further decrease the suspend current by set the SUSP2 (bit4 of the UCC). When the resume signal is sent out by the host, the HT82A821R will wake up the MCU by USB interrupt and Rev. 1.10 the Resume line (bit 3 of USC) is set. In order to make ...
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... USB Interface The HT82A821R have 3 Endpoints (EP0 ~EP2). EP0 supports Control transfer. EP1 supports Interrupt transfer. EP2 supports Isochronous transfer. These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H ), SIES (25H), MISC (26H), SETIO (27H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH) used for the USB function. ...
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... UCC (22H) Register Functions 0 USB remote-wake-up enable/disable (1/0) 0 USB device address AWR (23H) Register Functions Set by users when related USB endpoints were stalled. They are 0 cleared by USB reset and Setup Token event. 0 Undefined bit, read STALL (24H) Register 17 HT82A821R June 29, 2007 ...
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... To show that the data in FIFO is setup command. This bit will last this state until next one entering the FIFO. To tell that the desired FIFO is ready to work. To tell that host sent a 0-sized packet to MCU. This bit must be cleared by read action to corresponding FIFO. USB MISC (26H) Register 18 HT82A821R June 29, 2007 ...
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... Functions 19 HT82A821R Result (dB) USVC 24 101_1100 101_1011 25 26 101_1010 101_1001 27 28 101_1000 101_0111 29 101_0110 30 101_0101 31 101_0100 32 June 29, 2007 ...
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... Undefined bit, read DAC write trigger bit DAC_WR (2FH) Register ;Save WDTS value ;Enter DAC Write Data mode, high nibble of WDTS=0101b ;Set DAC data low byte=00H ;Set DAC data high byte=80H ;Restore WDTS value ;Quit DAC Write Data mode 20 HT82A821R Functions June 29, 2007 ...
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... No. 1 PA0~PA7 pull-high resistor enabled or disabled (by bit) 2 LVR enable or disable 3 WDT enable or disable 4 WDT clock source WDTOSC SYS 5 CLRWDT instruction(s PA0~PA7 wake-up enabled or disabled (by bit) 7 TBHP enable or disable (default disable) Application Circuits Rev. 1.10 Options 21 HT82A821R June 29, 2007 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 22 HT82A821R June 29, 2007 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 23 HT82A821R Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 Description 24 HT82A821R Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.10 25 HT82A821R June 29, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.10 addr 26 HT82A821R June 29, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT82A821R June 29, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.10 addr 28 HT82A821R June 29, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.10 Stack Stack Stack [m]. 0~6) 29 HT82A821R June 29, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.10 [m]. 0~6) 30 HT82A821R June 29, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.10 [ HT82A821R June 29, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.10 0 [m] [ HT82A821R June 29, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.10 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 33 HT82A821R June 29, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.10 34 HT82A821R June 29, 2007 ...
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... Package Information 24-pin SSOP (150mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 228 150 8 335 HT82A821R Max. 244 157 12 346 June 29, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.10 Dimensions in mil Min. Nom. 394 290 14 590 HT82A821R Max. 419 300 20 614 104 June 29, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 37 HT82A821R June 29, 2007 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 Dimensions in mm 16+0.3 0.1 8 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 6.5 0.1 9.5 0.1 2.1 0.1 0.3 0.05 13.3 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4 0.1 2 0.1 10.9 0.1 15.9 0.1 3.1 0.1 0.35 0.05 21.3 38 HT82A821R June 29, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 39 HT82A821R June 29, 2007 ...