71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 69

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in
and a sequence of data bytes. A multi byte transaction is three or more bytes.
v1.0
(From Host) SPI_CSZ
(From Host) SPI_CSZ
Command Sequence
ADDR 1xxx xxxx STATUS
Byte0 ... ByteN
0xxx xxxx ADDR Byte0 ...
ByteN
Name
EX_SPI
SPI_CMD
SPI_E
IE_SPI
SPI_SAFE
(From 6543) SPI_DO
(From 6543) SPI_DO
(From Host) SPI_CK
(From Host) SPI_CK
SERIAL READ
SERIAL WRITE
(From Host) SPI_DI
(From Host) SPI_DI
Figure
x
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations
SFR FD[7:0]
SFR F8[7]
Location
270C[4]
270C[3]
A15
2701[7]
A15
0
0
23, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
A14
A14
16 bit Address
16 bit Address
A1
A1
© 2008–2011 Teridian Semiconductor Corporation
Rst
HI Z
HI Z
0
–
1
0
0
15
15
Description
Read data starting at ADDR. ADDR is auto-incremented until SPI_CSZ
is raised. Upon completion, SPI_CMD (SFR 0xFD) is updated to 1xxx xxxx
and an SPI interrupt is generated. The exception is if the command
byte is 1000 0000. In this case, no MPU interrupt is generated and
SPI_CMD is not updated.
Write data starting at ADDR. ADDR is auto-incremented until SPI_CSZ is
raised. Upon completion, SPI_CMD is updated to 0xxx xxxx and an SPI
interrupt is generated. The exception is if the command byte is 0000
0000. In this case, no MPU interrupt is generated and SPI_CMD is not
updated.
A0
A0
Table 58: SPI Command Sequences
16
16
C7
C7
Wk
0
–
1
0
0
C6
C6
8 bit CMD
8 bit CMD
Table 59: SPI Registers
C5
R/W
R/W
R/W
R/W
C5
Dir
R
23
23
C0
Description
SPI interrupt enable bit.
SPI command. The 8-bit command from the bus master.
SPI port enable bit. It enables the SPI interface on pins
SEGDIO36 – SEGDIO39.
SPI interrupt flag. Set by hardware, cleared by writing a 0.
Limits SPI writes to SPI_CMD and a 16 byte region in
DRAM when set. No other write operations are permitted.
C0
ST7
ST7
24
24
ST6
ST6
Status Byte
Status Byte
ST5
ST5
ST0
ST0
31
31
D7
32
32
D7
x
D6
D6
DATA[ADDR]
DATA[ADDR]
D1
D1
71M6543F/H Data Sheet
D0
D0
39
39
40
D7
40
D7
Extended Read . . .
Extended Write . . .
D6
D6
DATA[ADDR+1]
DATA[ADDR+1]
D1
D1
D0
D0
47
47
x
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