71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 103

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

5.2
Table 71
Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and
copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The
remaining bits are mapped to the address space 0x2XXX. Bits with R (read) direction can be read by the MPU. Columns labeled Rst and Wk
describe the bit values upon reset and wake, respectively. No entry in one of these columns means the bit is either read-only or is powered by the
NV supply and is not initialized. Write-only bits return zero when they are read.
Locations that are shaded in grey are non-volatile (i.e., battery-backed).
v1.0
Name
ADC_E
ADC_DIV
BCURR
BSENSE[7:0]
CE_E
CE_LCTN[5:0]
CHIP_ID[15:8]
CHIP_ID[7:0]
CHOP_E[1:0]
I/O RAM Map – Alphabetical Order
lists I/O RAM bits and registers in alphabetical order.
Location Rst Wk Dir
2885[7:0]
2109[5:0] 31 31 R/W
2300[7:0]
2301[7:0]
2106[3:2]
2704[4]
2200[5]
2704[3]
2106[0]
0
0
0
–
0
0
0
0
0
0
0
–
0
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
Table 71: I/O RAM Map – Alphabetical Order
R
R
R
Description
Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
The resulting ADC and FIR clock is as shown below.
Connects a 100 µA load to the battery selected by TEMP_BSEL.
The result of the battery measurement.
See
CE enable.
CE program location. The starting address for the CE program is 1024*CE_LCTN.
These bytes contain the chip identification.
Chop enable for the reference bandgap circuit. The value of CHOP changes on the
rising edge of the internal MUXSYNC signal according to the value in CHOP_E[1:0]:
1
00 = toggle
except at the mux sync edge at the end of an accumulation interval.
2.5.7 71M6543F/H Battery Monitor
0 = MCK/4
1 = MCK/8
1
01 = positive
ADC_DIV = 0
ADC_DIV = 1
MCK
10 = reversed
PLL_FAST = 0
6.291456 MHz
1.572864 MHz
0.786432 MHz
on page 56.
11 = toggle
19.660800 MHz
PLL_FAST = 1
4.9152 MHz
2.4576 MHz
71M6543F/H Data Sheet
103