71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 58

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

71M6543F/H Data Sheet
Bit Banged Optical UART (Third UART)
As shown in
signal in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port
is driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used
when the two dedicated UARTs must be connected to high speed clients and a slower optical UART is
permissible.
2.5.10 Digital I/O and LCD Segment Drivers
2.5.10.1 General Information
The 71M6543F/H combines most DIO pins with LCD segment drivers. Each SEG/DIO pin can be
configured as a DIO pin or as a segment driver pin (SEG).
On reset or power-up, all DIO pins are DIO inputs (except for SEGDIO0-15, see caution note below) until
they are configured as desired under MPU control. The pin function can be configured by the I/O RAM
registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1
configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO.
Once a pin is configured as DIO, it can be configured independently as an input or output. For SEGDIO0
to SEGDIO15, this is done with the SFR registers P0 (SFR 0x80), P1 (SFR 0x90), P2 (SFR 0xA0) and P3
(SFR 0xB0), as shown in
Example: SEGDIO12 (pin 32 in
writing 0 to bit 4 of LCD_MAP[15:8], and writing 1 to both P3[4]and P3[0]. The same pin is configured
as an LCD driver by writing 1 to bit 4 of LCD_MAP[15:8]. The display information is written to bits 0 to 5
of LCD_SEG12.
The PB pin is a dedicated digital input and is not part of the SEGDIO system.
A 3-bit configuration word, I/O RAM register DIO_Rn (I/O RAM 0x2009[2:0] through 0x200E[6:4]) can be
used for pins SEGDIO2 through SEGDIO11 (when configured as DIO) and PB to individually assign an
internal resource such as an interrupt or a timer control (DIO_RPB[2:0], I/O RAM 0x2450[2:0], configures
the PB pin). This way, DIO pins can be tracked even if they are configured as outputs.
internal resources which can be assigned using DIO_R2[2:0] through DIO_R11[2:0] and DIO_RPB[2:0]. If
more than one input is connected to the same resource, the resources are combined using a logical OR.
58
PORT_E.
The CE features pulse counting registers and each pulse counter interrupt output is internally
routed to the pulse interrupt logic. Thus, no routing of pulse signals to external pins is required in
order to generate pulse interrupts. See interrupt source No. 2 in
After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are
configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting
disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After
Figure
15, the 71M6543F/H can also be configured to drive the optical UART with a DIO
UART1_TX
DIO5
Table
OPT_BB
© 2008–2011 Teridian Semiconductor Corporation
0
1
0
1
UART1_RX
48.
OPT_TXINV
OPT_TXMOD=0
Table
Figure 15: Optical Interface (UART1)
OPT_TXMOD
DIO55
OPT_FDC
48) is configured as a DIO output pin with a value of 1 (high) by
A
OPT_RXDIS
1
0
EN
MOD
2
DUTY
VARPULSE
WPULSE
DIO51
B
2
0
3
1
OPT_TXE[1:0]
A
B
SEG55
SEG51
SEG5
OPT_FDC=2 (25%)
OPT_TXMOD=1,
LCD_MAP[51]
LCD_MAP[5]
LCD_MAP[55]
1
0
1
0
1
0
1/38kHz
Internal
Figure
SEGDIO55/
OPT_RX
SEGDIO51/
OPT_TX
SEGDIO5/TX2
12.
V3P3
Table 48
lists the
v1.0