71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 60

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows:
Thus, a total of 51 DIO pins are available with minimum LCD configuration, and a total of 56 LCD pins are
available with minimum DIO configuration.
71M6543F/H Data Sheet
The configuration for pins SEGDIO16 to SEGDIO31 is shown in
SEGDIO32 to SEGDIO45 is shown in
shown in Table 51.
60
SEGDIO
Pin #
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Configuration:
0 = DIO, 1 = LCD
SEG Data Register
DIO Data Register
Direction Register:
0 = input, 1 = output
Internal Resources
Configurable
(see
Table
SEGDIO
Table 48: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15
o
o
o
o
Pin #
SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins)
SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins)
3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK,
SEG50/E_RST)
2 SEG pins combined with the test multiplexer outputs (SEG46/TMUX2OUT,
SEG47/TMUXOUT)
47)
Table 49: Data/Direction Registers for SEGDIO16 to SEGDIO31
45
0
0
0
0
4
–
16
28
16
16
16
0
P0 (SFR 0x80)
P0 (SFR80)
© 2008–2011 Teridian Semiconductor Corporation
LCD_MAP[7:0] (I/O RAM 0x240B)
LCD_SEG0[5:0] to LCD_SEG15[5:0] (I/O RAM 0x2410[5:0] to 0x241F[5:0]
44
LCD_MAP[23:16] (I/O RAM 0x2409)
1
1
1
1
5
–
17
27
17
17
17
1
43
Y
2
2
2
2
6
18
25
18
18
18
2
Table
42
Y
3
3
3
3
7
19
24
19
19
19
3
50. The configuration for pins SEGDIO51 to SEGDIO55 is
41
Y
4
4
4
0
4
20
23
20
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
20
20
4
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
P1 (SFR 0x90)
P1 (SFR 0x90)
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
39
5
Y
5
5
1
5
(I/O RAM 0x2420[0] to 0x242F[0])
(I/O RAM 0x2420[1] to 0x242F[1])
21
22
21
21
21
5
38
Y
6
6
6
2
6
22
21
22
22
22
6
37
Y
7
7
7
3
7
23
20
23
23
23
7
Table
36
8
Y
0
8
0
4
24
19
24
24
24
0
P2 (SFR 0xA0)
P2 (SFR 0xA0)
LCD_MAP[15:8] (I/O RAM 0x240A)
49, and the configuration for pins
35
LCD_MAP[31:24] (I/O RAM 0x2408)
Y
9
1
9
1
5
25
18
25
25
25
1
10
34
10
26
17
26
26
26
2
2
6
Y
2
27
16
27
27
27
11
33
11
Y
3
3
3
7
28
11
28
28
28
12
32
12
4
4
0
4
–
P3 (SFR 0xB0)
P3 (SFR 0xB0)
29
10
29
29
29
13
31
13
5
5
1
5
–
14
30
30
30
30
30
14
9
6
6
2
6
–
v1.0
15
29
15
31
31
31
31
8
7
3
7
–
7