mc9328mx1 Freescale Semiconductor, Inc, mc9328mx1 Datasheet - Page 33

• Manufacturer Part Number: mc9328mx1
• Description: Arm9 Microprocessor
• Manufacturer: Freescale Semiconductor, Inc

Table 14. DTACK WAIT Read Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
4.4.2.3
Freescale Semiconductor
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
Number
Number
12
1
2
3
4
5
6
(output from
i.MX1)
OE
DATABUS
Address
(logic high)
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
CS5
RW
EB
Wait pulse width
CS5 assertion time
EB assertion time
CS5 pulse width
RW negated before CS5 is negated
RW negated to Address inactive
Wait asserted after CS5 asserted
WAIT
WAIT Write Cycle without DMA
1
2
Characteristic
9
programmable
min 0ns
programmable
min 0ns
Characteristic
11
Figure 8. WAIT Write Cycle without DMA
MC9328MX1 Technical Data, Rev. 7
6
3
12
See note 2
See note 2
Minimum
2.5T-0.29
67.28
3T
–
Minimum
1T
Functional Description and Application Information
7
3.0 ± 0.3 V
8
3.0 ± 0.3 V
4
10
5
Maximum
2.5T+0.68
Maximum
1020T
1020T
–
–
–
–
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
33