mc9328mx1 Freescale Semiconductor, Inc, mc9328mx1 Datasheet

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... The MC9328MX1 (i.MX1) processor features the advanced and power-efficient ARM920T™ core that operates at speeds up to 200 MHz. Integrated modules, which include a USB device, an LCD controller, and an ...

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... Interrupt AIPI 1 VMMU Controller DMAC Bus AIPI 2 (11 Chnl) Control EIM & eSRAM SDRAMC (128K) Figure 1. i.MX1 Functional Block Diagram MC9328MX1 Technical Data, Rev. 7 Standard System I/O GPIO PWM Timer 1 & 2 RTC Watchdog Multimedia Multimedia Accelerator Video Port Human Interface Analog Signal ...

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... Table 1. Ordering Information Temperature Solderball Type 0°C to 70°C Pb-free -30°C to 70°C Pb-free 0°C to 70°C Pb-free -30°C to 70°C Pb-free -40°C to 85°C Pb-free MC9328MX1 Technical Data, Rev. 7 Introduction based Order Number MC9328MX1VM20(R2) MC9328MX1DVM20(R2) MC9328MX1VM15(R2) MC9328MX1DVM15(R2) MC9328MX1CVM15(R2) 3 ...

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... SDBA [4:0] SDRAM non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM cycles. 4 Table 2. i.MX1 Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) Bootstrap SDRAM Controller MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... Test Clock to synchronize test logic and control register access through the JTAG port. TMS Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of TCK. Freescale Semiconductor Function/Notes Clocks and Resets JTAG MC9328MX1 Technical Data, Rev. 7 Signals and Connections 5 ...

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... Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated signal). REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). SIM_CLK SIM Clock SIM_RST SIM Reset SIM_RX Receive Data 6 Function/Notes DMA ETM CMOS Sensor Interface LCD Controller SIM MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... SPI2 Master TxData Output—This signal is multiplexed with a GPI/O pin yet shows primary or alternative signal in the signal multiplex scheme table. Please refer to the SPI and GPIO chapters in the MC9328MX1 Reference Manual for information about how to bring this signal to the assigned pin. SPI2_RXD SPI2 Master RxData Input— ...

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... Data Set Ready UART3_RI Ring Indicator UART3_DCD Data Carrier Detect UART3_DTR Data Terminal Ready Serial Audio Port – SSI (configurable to I SSI_TXDAT Transmit Data SSI_RXDAT Receive Data 8 Function/Notes Memory Stick Interface UARTs – IrDA/Auto-Bauding 2 S protocol) MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... Negative resistance input (b) RVP Positive reference for pen ADC RVM Negative reference for pen ADC AVDD Analog power supply AGND Analog ground BT1 I/O clock signal BT2 Output BT3 Input Freescale Semiconductor Function/Notes PWM ASP BlueTooth MC9328MX1 Technical Data, Rev. 7 Signals and Connections 9 ...

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... Function/Notes Test Function ® registered trademark of National Semiconductor.) Digital Supply Pins Supply Pins – Analog Modules Internal Power Supply Table 6 allows the user to select the function of each pin by MC9328MX1 Technical Data, Rev. 7 Table 6 on page 23 to configure the Freescale Semiconductor ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD1 K8 NVDD1 Static NVDD1 B1 A24 O NVDD1 C2 D31 I/O 69K NVDD1 C1 A23 O NVDD1 D2 D30 I/O 69K NVDD1 D1 A22 O NVDD1 D3 D29 I/O 69K NVDD1 E2 A21 O NVDD1 E3 D28 I/O 69K NVDD1 E1 A20 O NVDD1 F2 D27 I/O 69K ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD1 G5 D21 I/O 69K NVDD1 H1 A13 O NVDD1 H4 D20 I/O 69K T1 VSS Static QVDD1 H9 QVDD1 Static H8 VSS Static NVDD1 J5 NVDD1 Static NVDD1 J1 A12 O NVDD1 J4 D19 I/O 69K NVDD1 J2 A11 O NVDD1 J3 D18 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD1 NVDD1 M3 D11 I/O 69K NVDD1 P3 EB0 O NVDD1 N3 D10 I/O 69K NVDD1 NVDD1 N2 EB1 O NVDD1 P2 D9 I/O 69K NVDD1 R1 EB2 O M6 VSS Static NVDD1 H6 NVDD1 Static NVDD1 T2 A2 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD1 T6 CS1 O NVDD1 T7 CS0 O NVDD1 R6 D5 I/O 69K NVDD1 P6 ECB I NVDD1 N6 D4 I/O 69K NVDD1 R7 LBA O NVDD1 P8 D3 I/O 69K NVDD1 R8 BCLK NVDD1 P7 D2 I/O 69K J7 VSS Static NVDD1 L6 NVDD1 Static ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD1 T10 SDWE O NVDD1 R11 SDCKE0 O NVDD1 P10 SDCKE1 O NVDD1 N10 RESET_SF O NVDD1 T11 CLKO O L7 VSS Static AVDD1 T12 AVDD1 Static AVDD1 M10 RESET_IN I 69K AVDD1 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD2 R14 TDO O NVDD2 N15 TMS I 69K NVDD2 L9 TCK I 69K NVDD2 N16 TDI I 69K NVDD2 P14 I2C_SCL O NVDD2 P15 I2C_SDA I/O NVDD2 N13 CSI_PIXCLK I NVDD2 M13 CSI_HSYNC I NVDD2 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD2 K12 LD12 O QVDD3 J15 QVDD3 Static J16 VSS Static NVDD2 K9 NVDD2 Static NVDD2 J14 LD11 O NVDD2 K11 LD10 O NVDD2 H15 LD9 O NVDD2 J13 LD8 O NVDD2 J12 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up J9 VSS Static 6 E16 R2A I QVDD 6 D16 R2B I QVDD 6 F14 PX1 I QVDD 6 F13 PY1 I QVDD 6 E15 PX2 I QVDD 6 E14 PY2 I QVDD 6 D15 R1A I QVDD C16 R1B I 6 QVDD ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up 6 D12 NC O QVDD QVDD4 A13 QVDD4 Static B13 VSS Static BTRFVDD C12 BTRFVDD Static BTRFVDD B12 BT1 I BTRFVDD F11 BT2 O BTRFVDD A12 BT3 I BTRFVDD E11 BT4 I BTRFVDD ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD3 C9 UART1_TXD O NVDD3 A8 UART1_RTS I NVDD3 G8 UART1_CTS O NVDD3 B8 SSI_TXCLK I/O NVDD3 F8 SSI_TXFS I/O NVDD3 E8 SSI_TXDAT O NVDD3 D8 SSI_RXDAT I NVDD3 B7 SSI_RXCLK I/O NVDD3 C8 SSI_RXFS I/O A7 VSS Static NVDD4 C7 UART2_RXD I NVDD4 F7 UART2_TXD O NVDD4 E7 UART2_RTS I NVDD4 ...

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... Table 3. MC9328MX1 Signal Multiplexing Scheme (Continued) Primary I/O Supply BGA Voltage Pin Signal Dir Pull-up NVDD4 F6 SIM_RST O NVDD4 G6 SIM_RX I NVDD4 B4 SIM_TX I/O NVDD4 C4 SIM_PD I NVDD4 D4 SIM_SVEN O NVDD4 B3 SD_CMD I/O NVDD4 A3 SD_CLK O NVDD4 A2 SD_DAT3 I/O NVDD4 E5 SD_DAT2 I/O NVDD4 B2 SD_DAT1 I/O NVDD4 C3 SD_DAT0 I/O 1 After reset, CS0 goes H/L depends on BOOT[3:0]. ...

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... AVDD pins from other VDD pins. BTRFVDD is the supply voltage for the Bluetooth interface signals quite sensitive to the data transmit/receive accuracy. Please refer to Bluetooth RF spec for special handling. If Bluetooth is not used 22 Table 4. Maximum Ratings Rating MC9328MX1 Technical Data, Rev. 7 Minimum Maximum Unit -0.3 3 ...

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... Sidd Standby current 2 (Core = 150 MHz, QVDD = 1.8V, temp = 55 Sidd Standby current 3 (Core = 150 MHz, QVDD = 2.0V, temp = 25 Freescale Semiconductor Table 5. Recommended Operating Range Rating Parameter ° C) ° C) ° C) MC9328MX1 Technical Data, Rev. 7 Electrical Characteristics Table 2 on page 4. Minimum Maximum 0 70 -30 70 -40 85 2.70 3.30 1.70 3.30 1.70 1.90 1 ...

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... EXTAL32k startup time 24 Parameter ° 2.0 mA) = -2.5 mA under an operating temperature from T DD min DD max Table 7. Tristate Signal Timing Parameter Table 8. 32k/16M Oscillator Signal Timing Minimum – 800 MC9328MX1 Technical Data, Rev. 7 Min Typical Max – 60 – 0.7V – Vdd+0.2 DD – – 0.4 0.7V – Vdd DD – ...

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... Functional Description and Application Information Minimum 1 – TBD Figure 2. See Table Valid Data 4a Figure 2. Trace Port Timing Diagram MC9328MX1 Technical Data, Rev. 7 RMS Maximum Unit TBD TBD – – – – for the ETM9 timing parameters used 1 Valid Data 4b 25 ...

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... Table 10. In this table reference clock period after the ref Table 10. DPLL Specifications Test Conditions Minimum MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Maximum 0 100 MHz 2 – – ns – – – ...

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... RESET_DRAM HRESET RESET_OUT CLK32 HCLK Freescale Semiconductor Table 10. DPLL Specifications (Continued) Test Conditions = MHz, Vcc = 1.8V NOTE 1 10% AVDD 2 Exact 300ms Figure 3. Timing Relationship with POR MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Minimum Typical Maximum 1.0 – 1.5 (10%) 1.7 – 2.5 – – 4 ...

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... The timing diagram for the EIM is shown in Figure 5, and 28 5 1.8 ± 0.1 V Min 1 note 300 Table 12 defines the parameters of signals. MC9328MX1 Technical Data, Rev cycles @ CLK32 4 3.0 ± 0.3 V Unit Max Min Max – 1 – – note 300 300 300 ms ...

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... Figure 5. EIM Bus Timing Diagram Table 12. EIM Bus Timing Parameter Table 1.8 ± 0.1 V Min Typical 2.48 3.31 1.55 2.48 2.69 3.31 1.55 2.48 1.35 2.79 1.86 2.59 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 10a 3.0 ± 0.3 V Max Min Typical Max 9.11 2.4 3.2 8 ...

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... The signal values and units of measure for this figure are found in the associated tables. 30 1.8 ± 0.1 V Min Typical Max 2.32 2.62 6.85 2.11 2.52 6.55 2.38 2.69 7.04 2.17 2.59 6.73 1.91 2.52 5.54 1.81 2.42 5.24 1.97 2.59 5.69 1.76 2.48 5.38 2.07 2.79 6.73 1.97 2.79 6.83 1.91 2.62 6.45 1.61 2.62 5.64 1.61 2.62 5.84 1.55 2.48 5.59 1.55 2.59 5.80 5.54 – 0 – 1.81 2.72 6.85 1.45 2.48 5.69 1.63 – 2.52 – MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Min Typical Max 2.3 2.6 6.8 ns 2.1 2.5 6.5 ns 2.3 2.6 6.8 ns 2.1 2.5 6.5 ns 1.9 2.5 5.5 ns 1.8 2.4 5.2 ns 1.9 2.5 5.5 ns 1.7 2.4 5.2 ns 2.0 2.7 6.5 ns 1.9 2.7 6.6 ns 1.9 2.6 6.4 ns 1.6 2.6 5.6 ns 1.6 2.6 5.8 ns 1.5 2.4 5.4 ns 1.5 2.5 5.6 ns – ...

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... The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. Freescale Semiconductor Figure 6. WAIT Read Cycle without DMA Minimum See note 2 56.81 2T+2.2 T-1.86 1.5T+0.24 0.5 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0 ± 0.3 V Maximum – 3T – – – 1020T 3T+7.17 – ...

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... CS deactive to next CS active 10 OE negate after EB negate 11 Wait becomes low after CS5 asserted Minimum See note 2 3T 1.5T+0.24 – – 2T+2.2 T-1.86 – T 0.5 0 MC9328MX1 Technical Data, Rev 3.0 ± 0.3 V Unit Maximum – ns – ns 1.5T+0.85 ns 0.93 ns 1020T ns 3T+7.17 ns – – ...

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... Wait asserted after CS5 asserted Freescale Semiconductor Minimum Figure 8. WAIT Write Cycle without DMA Minimum See note 2 See note 2 3T 2.5T-0.29 67.28 – MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0 ± 0.3 V Maximum 1T 1020T 3.0 ± 0.3 V Maximum – – – ...

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... CS5 2 programmable min 0ns (logic high) WAIT 9 DATABUS 34 Minimum 1T+2.15 2.5T-1.18 – 1.5T+0. Figure 9. WAIT Write Cycle DMA Enabled MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Maximum 2T+7.34 – T 1.5T+2.35 1019T 1020T Freescale Semiconductor Unit ...

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... Figure 5, and Table 12 defines the parameters of signals. Freescale Semiconductor Functional Description and Application Information Minimum See note 2 See note 2 3T 2.5T-0.29 – – T+2.15 24.87 – T 1.5T+0. MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Maximum – – – 2.5T+0.68 0.93 1020T 2T+7.34 – T – 1.5T+2.35 1019T 1020T ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register 36 Seq/Nonseq Read V1 Last Valid Data Last Valid Address Read Figure 10. WSC = 1, A.HALF/E.HALF MC9328MX1 Technical Data, Rev Freescale Semiconductor ...

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... BCLK (burst clock) Last Valid Address ADDR CS0 R/W LBA OE EB DATA Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor Nonseq Write V1 Write Data (V1) Last Valid Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Unknown V1 Write Write Data (V1) 37 ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF 38 Read V1 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK (burst clock) ADDR Last Valid Addr CS0 R/W LBA OE EB DATA Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word 39 ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF 40 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS3 R/W LBA OE EB DATA Last Valid Data Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word 41 ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF 42 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Address 2/2 Half Word 43 ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF 44 Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MX1 Technical Data, Rev Word Address 2/2 Half Word 45 ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 46 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MX1 Technical Data, Rev. 7 Unknown Address 2/2 Half Word 47 ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 48 Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Read Idle Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Write Write Data Read Data Address V8 Write Write Data 49 ...

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... BCLK (burst clock) ADDR Last Valid Addr CS R/W LBA OE EB DATA Last Valid Data Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 50 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MX1 Technical Data, Rev. 7 Address Write Data (2/2 Half Word) Freescale Semiconductor ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Write Data Read Data Address V8 Write Write Data 51 ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 52 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MX1 Technical Data, Rev. 7 Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

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... Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Idle Nonseq Write V8 Last Valid Data Address V1 CNC Read Read Data Last Valid Data MC9328MX1 Technical Data, Rev. 7 Write Data Read Data Address V8 Write Write Data 53 ...

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... ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF 54 Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MX1 Technical Data, Rev. 7 Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Functional Description and Application Information Seq Seq Read Read Word V2 Word Address V1 Read V1 Word V2 Word MC9328MX1 Technical Data, Rev. 7 Idle Seq Read V4 V3 Word V4 Word V3 Word V4 Word 55 ...

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... DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 56 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MX1 Technical Data, Rev. 7 Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read V1 1/2 MC9328MX1 Technical Data, Rev. 7 Idle Seq Read V2 V1 Word V2 Word V1 2/2 ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 58 Last Valid Data Address V1 Read V1 1/2 MC9328MX1 Technical Data, Rev. 7 Idle Seq Read V2 V1 Word V2 Word V1 2/2 ...

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... Table 18 through Table 18. Pen ADC System Performance 1 Full Range Resolution 1 Non-Linearity Error 1 Accuracy Tested under input = 0~1.8V at 25°C MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Actual Value Unit 1, 2 HWAIT2+2 Tpix HWIDTH+1 Tpix 0 ≤ T3 ≤ – ...

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... Minimum Typical – 32768 – – 13.65 – 8 – 8 – Negative QVDD – 10 MC9328MX1 Technical Data, Rev. 7 Maximum Unit – – – 8199 – – – 33% – 9 – Bits 0 – Bits 9 – Bits – ...

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... Where V is input output the slope, and C is the y-intercept. Nominal Gain G = 65535 / 4800 = 13.65mV 0 Nominal Offset C = 65535 / 2 = 32767 0 Freescale Semiconductor Functional Description and Application Information Sample 65535 Smax C0 1800 Figure 34. Gain Calculations -1 Sample 65535 Smax C0 1800 Figure 35. Offset Calculations -1 MC9328MX1 Technical Data, Rev 2400 G0 Vi 2400 61 ...

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... Figure 37 and Figure 62 Sample 65535 Smax C0 Figure 36. Gain Error Calculations = (65535 - (65535 - 32767) / 1800 = 18. max 0 = (18.20 - 13.65) / 13.65 * 100% = 33% CAUTION 38, and the associated parameters shown in MC9328MX1 Technical Data, Rev. 7 Gmax G0 Vi 2400 1800 / 1800 * 100% 0 Table 22 and Table Freescale Semiconductor 23. ...

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... The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register (0x00216050) and RF_Status (0x0021605C) registers. Freescale Semiconductor Parameter MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Receive Transmit 8 Minimum Typical Maximum – 4 – – 12 – – 6 – ...

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... FIFO. Figure 39 different triggering mechanisms Parameter through Figure 43 show the timing relationship of the master SPI using MC9328MX1 Technical Data, Rev Minimum Maximum Unit 15 – ...

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... SS (input) SCLK, MOSI, MISO Figure 42. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 43. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Freescale Semiconductor Functional Description and Application Information MC9328MX1 Technical Data, Rev ...

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... Ref No. 8 SCLK frequency 9 SCLK pulse width 4.9 LCD Controller This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MX1 Reference Manual. LSCLK LD[15:0] 66 Figure 39 Parameter Minimum 3 • ...

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... V Minimum – Non-display XMAX T8 (1,1) (1,2) T9 T10 Minimum T5+T6 +T7+T9 XMAX MC9328MX1 Technical Data, Rev. 7 Maximum Unit 2 ns Display region Line 1 Line Y T7 (1,X) Corresponding Register Value (VWAIT1·T2)+T5+T6+T7+T9 XMAX+T5+T6+T7+T9+T10 VWIDTH·(T2) VWAIT2·(T2) HWIDTH+1 HWAIT2+1 HWAIT1+1 Unit ...

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... CMD_DAT Input CMD_DAT Output Figure 47. Chip-Select Read Cycle Timing Diagram 68 Minimum - Valid Data 7 Valid Data 6a MC9328MX1 Technical Data, Rev. 7 Corresponding Register Value Unit Figure 46, all 3 signals Valid Data Valid Data 6b Freescale Semiconductor ns Ts ...

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... For the card address assignment, ID Figure 48. The symbols for Figure 48 Definition Symbol S Data bits T Repetition P E MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0 ± 0.3 V Minimum Maximum 0 25/5 0 400 – 10/50 – – 10/50 – – 10/50 3 – 10/50 3 – ...

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... Timing response end to next CMD start (data transfer mode) N cycles CC ****** CRC Timing of command sequences (all modes) until the card sees a stop transmission command. The AC MC9328MX1 Technical Data, Rev. 7 CID/OCR Content Identification Timing CID/OCR Content SET_RCA Timing and N ...

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... ***** Timing of stop command Valid Read Data (CMD12, data transfer mode) Figure 50. Timing Diagrams at Data Read MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information Response Content CRC E Z ***** Read Data ***** ***** Read Data N ...

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... Functional Description and Application Information The stop transmission command may occur when the card is in different states. different scenarios on the bus. 72 Figure 51. Timing Diagrams at Data Write MC9328MX1 Technical Data, Rev. 7 Figure 52 shows the Freescale Semiconductor ...

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... MMC/SD bus clock, CLK (All values are referred to minimum (VIH) and maximum (VIL) Command response cycle Identification response cycle Access time delay cycle Freescale Semiconductor Functional Description and Application Information Figure 48 through Symbol Minimum NCR 2 NID 5 NAC 2 MC9328MX1 Technical Data, Rev. 7 Figure 52 Maximum Unit 64 Clock cycles 5 Clock cycles TAAC + NSAC Clock cycles 73 ...

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... NCC 8 NWR 2 NST 2 Response Block Data Interrupt Period Figure 53. SDIO IRQ Timing Diagram MC9328MX1 Technical Data, Rev. 7 Figure 52 (Continued) Maximum Unit – Clock cycles – Clock cycles – Clock cycles 2 Clock cycles ****** IRQ S Block Data ...

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... BS1 bus states are automatically repeated to avoid a bus collision on the SDIO. Freescale Semiconductor CMD52 CRC Figure 54. SDIO ReadWait Timing Diagram MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information ****** Block Data S E Block Data E 75 ...

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... MS_SCLKO rise time 1 10 MS_SCLKO fall time 1 11 MS_BS delay time Figure 55. MSHC Signal Timing Diagram Parameter 1 1 MC9328MX1 Technical Data, Rev 3.0 ± 0.3 V Unit Minimum Maximum – 25 MHz 20 – – ...

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... Clock fall time Freescale Semiconductor Parameter 1,2 Table 32 Figure 56. PWM Output Timing Diagram 1.8 ± 0.1 V Minimum Maximum 3.3 – 7.5 – – 5 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0 ± 0.3 V Minimum Maximum – – – – – 3.0 ± ...

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... Figure 57. SDRAM Read Cycle Timing Diagram 78 1.8 ± 0.1 V Minimum Maximum – 6.67 5.7 – 5.7 – COL/ Data Note: CKE is high during the read/write cycle. MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Minimum Maximum – 5/ – – Freescale Semiconductor ...

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... Data out high-impedance time ( Data out high-impedance time ( Data out high-impedance time ( Active to read/write command period ( SDRAM clock cycle time. This settings can be found in the MC9328MX1 reference manual. RCD Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – ...

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... Precharge cycle period 7 Active to read/write command delay 8 Data setup time 9 Data hold time 1 Precharge cycle timing is included in the write timing diagram and t = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual. RP RCD ROW/BA 1.8 ± 0.1 V Minimum Maximum 2 ...

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... SDRAM clock cycle time 4 Address setup time 5 Address hold time 6 Precharge cycle period 7 Auto precharge command period 1 t and t = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference manual Freescale Semiconductor Figure 59. SDRAM Refresh Timing Diagram 1.8 ± 0.1 V Minimum Maximum 2 ...

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... Data moves across the USB in packets. Groups of packets are combined to form data transfers. The same packet transfer mechanism applies to bulk, interrupt, and control transfers. Isochronous data is also moved in the form of packets, however, because isochronous pipes are given a fixed portion of the USB bandwidth at all times, there is no end-of-transfer. 82 MC9328MX1 Technical Data, Rev. 7 Freescale Semiconductor ...

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... VPO_ROE USBD_VMO low to USBD_ROE deactivated (includes SE0) VMO_ROE SE0 interval of EOP FEOPT Data transfer rate PERIOD Freescale Semiconductor 6 t PERIOD 2 Parameter MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information t 4 VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0 ± 0.3 V Minimum Maximum 83.14 83.47 81.55 81.98 83.54 83 ...

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... The I C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. SDA SCL 84 Parameter Figure 63. Definition of Bus Timing for I MC9328MX1 Technical Data, Rev FEOPR 3.0 ± 0.3 V Unit Minimum Maximum 82 – ...

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... Table 38 Bus Timing Parameter Table 1.8 ± 0.1 V Minimum Maximum 182 0 11.4 80 480 182.4 Figure 67 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0 ± 0.3 V Minimum Maximum – 160 – 171 0 150 – 10 – – 120 – – 320 – ...

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... Figure 65. SSI Receiver Internal Clock Timing Diagram STCK Input STFS (bl) Input STFS (wl) Input STXD Output SRXD Input Note: SRXD Input in Synchronous mode only Figure 66. SSI Transmitter External Clock Timing Diagram MC9328MX1 Technical Data, Rev Freescale Semiconductor ...

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... STCK/SRCK clock period 16 STCK/SRCK clock high period 17 STCK/SRCK clock low period Freescale Semiconductor 1.8 ± 0.1 V Minimum 1 (Port C Primary Function 1.5 3 -1.2 3 2.5 3 0.1 3 1.48 3 -1.1 3 2.51 3 0.1 14.25 0.91 0.57 12.88 21 92.8 27.1 61.1 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 25 30 3.0 ± 0.3 V Maximum Minimum Maximum 2 ) – 83.3 – 4.5 1.3 3.9 -1.7 -1.1 -1.5 4.3 2.2 3.8 -0.8 0.1 -0.8 4.45 1.3 3.9 -1.5 -1.1 -1.5 4.33 2.2 3.8 -0.8 0.1 -0.8 15.73 12.5 13.8 3.08 0.8 2.7 3.19 0.5 2 ...

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... FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function bit length word length. 88 1.8 ± 0.1 V Minimum 3 – 3 – 3 – 3 – 3 – 3 – 3 – 3 – 18.01 8.98 9.12 18.47 1.14 0 15.4 0 1.14 0 MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Maximum Minimum Maximum 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 92.8 0 81.4 28.16 15.8 24.7 18.13 7 ...

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... Minimum Maximum 1 (Port B Alternate Function 95 – 1.7 4.8 -0.1 1.0 3.08 5.24 1.25 2.28 1.71 4.79 -0.1 1.0 3.08 5.24 1.25 2.28 14.93 16.19 1.25 3.42 2.51 3.99 12.43 14.59 20 – 0 – 92.8 – 27.1 – 61.1 – – 92.8 – 92.8 – 92.8 – 92.8 – 92.8 – 92.8 – 92.8 – 92.8 18.9 29.07 9.23 20.75 10.60 21.32 MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Unit Minimum Maximum 2 ) 83.3 – ns 1.5 4.2 ns -0.1 1.0 ns 2.7 4.6 ns 1.1 2.0 ns 1.5 4.2 ns -0.1 1.0 ns 2.7 4.6 ns 1.1 2.0 ns 13.1 14.2 ns 1.1 3.0 ns 2.2 3.5 ns 10.9 12.8 ns 17.5 – – 81.4 – ns 40.7 – ns 40.7 – ...

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... STCK high to STXD high 90 1.8 ± 0.1 V Minimum 17.90 1.14 0 18.81 0 1.14 0 1.8V +/- 0.10V Minimum 1 (Port C Alternate Function 1.7 3 -0.1 3 3.08 3 1.25 3 1.71 3 -0.1 3 3.08 3 1.25 14.93 1.25 MC9328MX1 Technical Data, Rev. 7 3.0 ± 0.3 V Maximum Minimum Maximum 29.75 15.7 26.1 – 1.0 – – 0 – – 16.5 – – 0 – – 1.0 – – 0 – 3.0V +/- 0.30V Maximum Minimum Maximum 2 – ...

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... STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Freescale Semiconductor 1.8V +/- 0.10V Minimum 2.51 12. 92.8 27.1 61.1 3 – 3 – – 3 – 3 – 3 – 3 – 3 – 18.9 9.23 10.60 17.90 1.14 0 18.81 0 1.14 0 MC9328MX1 Technical Data, Rev. 7 Functional Description and Application Information 3.0V +/- 0.30V Maximum Minimum Maximum 3.99 2.2 3.5 14.59 10.9 12.8 – 17.5 – – 0 – 2 – 81.4 – – 40.7 – – 40.7 – 92.8 0 81.4 92.8 0 81.4 92 ...

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... VSYNC HSYNC PIXCLK DATA[7:0] Figure 68. Sensor Output Data on Pixel Clock Falling Edge CSI Latches Data on Pixel Clock Rising Edge Valid Data Valid Data 3 4 MC9328MX1 Technical Data, Rev. 7 Figure 69 shows the timing diagram Table 42 Valid Data Freescale Semiconductor ...

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... Freescale Semiconductor Functional Description and Application Information 6 2 Valid Data Valid Data 3 4 Parameter Min 180 10.42 10.42 0 MC9328MX1 Technical Data, Rev Valid Data Max Unit – ns – ns – ns – ns – ns – ...

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... Valid Data Valid Data Valid Data Valid Data 2 3 Parameter Min 180 1 MC9328MX1 Technical Data, Rev. 7 Figure 71 shows the timing diagram Table 43 Valid Data Valid Data Max Unit – ns – ns Freescale Semiconductor ...

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... Falling-edge latch data max fall time allowed = (negative duty cycle - hold time) max rise time allowed = (positive duty cycle - setup time) Freescale Semiconductor Functional Description and Application Information Parameter Min 1 10.42 10.42 0 MC9328MX1 Technical Data, Rev. 7 Max Unit – ns – ns – MHz ...

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Pin-Out and Package Information Table 44 illustrates the package pin assignments for the 256-pin MAPBGA package. For a complete listing of signals, see the Signal Multiplexing Table 3 on page 11 USBD_ A NVSS ...

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... DIMENSIONS AND TOLERANCES PER ASME Y14 5M-1994. 3.MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. Figure 72. i.MXL 256 MAPBGA Mechanical Drawing Freescale Semiconductor Case Outline 1367 MC9328MX1 Technical Data, Rev. 7 Pin-Out and Package Information SIDE VIEW 97 ...

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... Reference Documents The following documents are required for a complete description of the MC9328MX1 and are necessary to design properly with the device. Especially for those not familiar with the ARM920T processor or previous i.MX processor products, the following documents are helpful when used in conjunction with this document ...

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... Freescale Semiconductor NOTES MC9328MX1 Technical Data, Rev ...

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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC9328MX1 Document Number: Rev. 7 12/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...