r5f3650kcnfb Renesas Electronics Corporation., r5f3650kcnfb Datasheet - Page 77

• Manufacturer Part Number: r5f3650kcnfb
• Description: M16c/65c Group Renesas Mcu
• Manufacturer: Renesas Electronics Corporation.

M16C/65C Group
R01DS0015EJ0100 Rev.1.00
Feb 07, 2011
Switching Characteristics
(V
Table 5.37
Notes:
CC1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD
h(RD-AD
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
d(DB-WR)
h(WR-DB)
5.2.4.2
1.
2.
3.
4.
Symbol
= V CC2 = 5 V, V
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = − CR × ln(1 − V
by a circuit of the right figure.
For example, when V
time of output low level is
t = − 30 pF × 1 k Ω × In(1 − 0.2V
Calculated according to the BCLK frequency as follows:
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
0.5 10
--------------------- - 10 ns
(
----------------------------------- - 40 ns
)
0.5 10
--------------------- - 20 ns
f
= 6.7 ns.
n 0.5
(
f
BCLK
(
–
)
BCLK
f
×
)
×
(
BCLK
)
) 10
9
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
)
In 1 to 3 Waits Setting and When Accessing External Area
Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
9
×
–
–
)
9
[
[
–
SS
]
]
OL
= 0 V, at T
[
/V
OL
]
CC2
= 0.2V
)
n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
When n = 1, f
opr
CC2
Parameter
CC2
= -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified)
/V
, C = 30 pF, R = 1 k Ω , hold
CC2
)
(BCLK)
(3)
is 12.5 MHz or less.
Figure 5.14
Measuring
Condition
See
(Note 2)
(Note 1)
(Note 4)
DBi
Min.
5. Electrical Characteristics
-4
0
0
0
0
0
Standard
V
CC1
Max.
= V
25
25
15
25
25
40
Page 77 of 109
C
R
CC2
Unit
= 5 V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns