tmp89fh42l TOSHIBA Semiconductor CORPORATION, tmp89fh42l Datasheet - Page 48

• Manufacturer Part Number: tmp89fh42l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.3
System clock controller
RB000
・ Start the IDLE0 and SLEEP0 modes
・ Release the IDLE0 and SLEEP0 modes
These modes are selected at the interrupt master enable flag (IMF), the individual interrupt enable
flag (EF5) for the time base timer and TBTCR<TBTEN>. After releasing the IDLE0 or SLEEP0
mode, SYSCR2<TGHALT> is automatically cleared to "0" and the operation mode is returned to
the mode preceding the IDLE0 or SLEEP0 mode. If TBTCR<TBTEN> has been set at "1", the
INTTBT interrupt latch is set.
and a reset by the voltage detection circuits. When a reset is released, the warm-up starts. After
the warm-up is completed, the NORMAL1 mode becomes active.
Stop (disable) the peripherals such as a timer counter.
To start the IDLE0 or SLEEP0 mode, set SYSCR2<TGHALT> to "1".
The IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
The IDLE0 and SLEEP0 modes are also released by a reset by the RESET pin, a power-on reset
(Normal release mode)
Figure 2-11 IDLE0 and SLEEP0 Modes
No
"0"
No
No
Execution of the instruction
which follows the IDLE0 or
Starting IDLE0 or SLEEP0
Stopping peripherals by
mode by an instruction
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SLEEP0 mode start
Interrupt processing
CPU and WDT stop
TBTCR<TBTEN>
TBT source clock
TBT interrupt
instructions
Reset input
instruction
falling edge
IMF = "1"
enabled
No
Yes
Yes
"1"
Yes
(Interrupt release mode)
Yes
Reset
TMP89FH42L