hip6301vcbza-t Intersil Corporation, hip6301vcbza-t Datasheet - Page 18

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hip6301vcbza-t

Manufacturer Part Number
hip6301vcbza-t
Description
Microprocessor Core Voltage Regulator Multiphase Buck Pwm Controller
Manufacturer
Intersil Corporation
Datasheet
MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the following
equations). The conduction losses are the main component
of power dissipation for the lower MOSFETs, Q2 and Q4 of
Figure 1. Only the upper MOSFETs, Q1 and Q3 have
significant switching losses, since the lower device turns on
and off into near zero voltage.
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
dissipated by the Driver IC and don't heat the MOSFETs.
However, large gate-charge increases the switching time,
t
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
A diode, anode to ground, may be placed across Q2 and Q4
of Figure 1. These diodes function as a clamp that catches
the negative inductor swing during the dead time between
the turn off of the lower MOSFETs and the turn on of the
upper MOSFETs. The diodes must be a Schottky type to
prevent the lossy parasitic MOSFET body diode from
conducting. It is usually acceptable to omit the diodes and let
the body diodes of the lower MOSFETs clamp the negative
inductor swing, but efficiency could drop one or two percent
as a result. The diode's rated reverse breakdown voltage
must be greater than the maximum input voltage.
P
P
SW
UPPER
LOWER
which increases the upper MOSFET switching losses.
=
=
I
----------------------------------------------------------- -
I
-------------------------------------------------------------------------------- -
O
O
2
2
×
×
r
r
DS ON
DS ON
V
(
(
IN
)
V
)
×
×
IN
V
(
V
OUT
18
IN
+
V
I
--------------------------------------------------------- -
OUT
O
×
V
)
IN
×
2
t
SW
×
F
SW
December 27, 2004
FN9034.2

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