hip6301vcbza-t Intersil Corporation, hip6301vcbza-t Datasheet - Page 10

• Manufacturer Part Number: hip6301vcbza-t
• Description: Microprocessor Core Voltage Regulator Multiphase Buck Pwm Controller
• Manufacturer: Intersil Corporation

For the first 32 PWM switching cycles, the DAC output
remains inhibited and the PWM outputs remain three stated.
From the 33rd cycle and for another, approximately 150 cycles
the PWM output remains low, clamping the lower output
MOSFETs to ground, see Figure 3. The time variability is due
to the error amplifier, sawtooth generator and comparators
moving into their active regions. After this short interval, the
PWM outputs are enabled and increment the PWM pulse
width from zero duty cycle to operational pulse width, thus
allowing the output voltage to slowly reach the CORE voltage.
The CORE voltage will reach its programmed value before the
2048 cycles, but the PGOOD output will not be initiated until
the 2048th PWM switching cycle.
The soft-start time or delay time, DT = 2048/F
oscillator frequency, F
160µs, the PWM outputs are held in a three state level as
explained above. After this period and a short interval described
above, the PWM outputs are initiated and the voltage rises in
10.08ms, for a total delay time DT of 10.24ms.
Figure 3 shows the start-up sequence as initiated by a fast
rising 5V supply, V
short rise to the three state level in PWM 1 output during first
32 PWM cycles.
Figure 4 shows the waveforms when the regulator is
operating at 200kHz. Note that the Soft-Start duration is a
function of the Channel Frequency as explained previously.
Also note the pulses on the COMP terminal. These pulses
are the current correction signal feeding into the comparator
input (see the Block Diagram on page 2).
Figure 5 shows the regulator operating from an ATX supply.
In this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising V
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING
DELAY TIME
AT 500kHz
CC,
SW
applied to the controller. Note the
, of 200kHz, the first 32 cycles or
10
CC
VIN = 12V
, the PMOS device
SW
. For an
HIP6301V, HIP6302V
HIP6301V, HIP6302V
PWM 1
OUTPUT
PGOOD
VCORE
5V
VCC
Note that Figure 5 shows the 12V gate driver voltage
available before the 5V supply to the controller has reached
its threshold level. If conditions were reversed and the 5V
supply was to rise first, the start-up sequence would be
different. In this case the controller may sense an
overcurrent condition due to charging the output capacitors.
The supply would then restart and go through the normal
Soft-Start cycle.
Dynamic VID
The HIP6301V and HIP6302V require up to two full clock
cycles to detect a change in the VID code. VID code
changes that are not valid for at least two cycles may or may
not be detected. Once detected, the controller waits an
additional two-cycle wait period to be certain the change is
stable. After the two-cycle wait period, the DAC begins
stepping toward the new VID setting in 25mV increments.
The DAC makes one 25mV step every two clock cycles. For
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
AT 200kHz
VIN = 5V, CORE LOAD CURRENT = 31A
DELAY TIME
FREQUENCY 200kHz
VIN = 12V
December 27, 2004
12V ATX
SUPPLY
PGOOD
VCORE
5 V ATX
SUPPLY
V COMP
PGOOD
VCORE
5V
VCC
FN9034.2