pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 33

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

4
The following registers may be accessed:
Table 8
Addressing the Direct Registers
Address A0
0
1
The chapters in this section cover the registers in detail.
4.1
Access: Write on address 0
Value after power up: FF
RC
TE
RI
SB
MI1/0
MO1/0
Semiconductor Group
Detailed Register Description
Mode Register (MOD)
DB 7
RC
Reset Connection memory; writing a zero to this bit causes the complete connection
memory to be overwritten with 200
maximum time for resetting the connection memory is 250 s.
Tristate Enable; this bit determines which tristating scheme is activated:
Reset Indirect access mechanism; setting this bit resets the indirect access
mechanism. RI has to be cleared before writing/reading IAR after reset.
Stand By; by selecting SB = 1 all outputs are tristated. The connection memory works
normally. The PEx 2045 can be activated immediately by resetting SB.
Input/Output operation Mode; these bits define MO1/0: the bit rate of the input and
output lines. The bit rates are given in table 9, the corresponding pin functions in
table 10 (standard configuration) and table 11 (primary multiplex access configuration).
TE = 1:
TE = 0:
Note:
H
If the speech memory address written into the connection memory
is S8 – S0 = 0, the output channel is tristated.
The S9 bit written into the connection memory is interpreted as a
validity bit: S9 = 0 enables the programmed connection, S9 = 1
tristates the output.
If TE = 1, time-slot 0 of the logical input line 0 cannot be used for
switching.
Write Operation
MOD
IAR
33
H
(tristate). During this time STA:B is set. The
Read Operation
STA
IAR
TE
DB 0
PEB 2045
PEF 2045