pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 20

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

Using the 3 signals A0, WR and RD the IAR, MOD and STA registers can be identified according
to table 3.
Table 3
Addressing of the Direct Registers
A0
0
1
The A0 address distinguishes between the IAR and the directly accessible registers. The WR and
RD strobes combined with an A0 equal to logical 0 identify the mode- and status registers,
respectively. The data bus contains the associated information. In the following paragraphs the
indirect register access and the register contents will be described.
Indirect Register Access (A0 = 1)
To perform an indirect register access 3 consecutive instructions have to be programmed. One
indirect register access has to be completed before the next one can begin. The 3 instructions of the
indirect access operate on the indirect access register. It receives, in sequence the control byte, the
data byte and the address byte according to table 4.
Table 4
IAR Byte Structure
Bit 7
0
D7
IA7
The data byte contains the information which shall be written into the connection memory or the
indirect registers, i.e. the CSR or the CFR. The address byte indicates which one of the indirect
registers shall be accessed or in which location of the CM the data shall be written. The control byte
determines whether the connection memory or one of the indirect registers shall be accessed and
whether a write or read operation shall be performed.
Before an indirect access is started, the Z- and B-bits of the status register must be 0. With the first
instruction the Z bit is set (see chapter 4.2). After the third instruction the PEx 2045 accesses the
physical register or memory location. This access requires maximally 900 ns. After the access
finishes the Z bit is reset. The 3 instructions are separated by intervals where both WR and RD are
in a high state.
Figure 13 illustrates a write operation on the IAR.
Semiconductor Group
0
D6
IA6
K1
D5
IA5
K0
D4
IA4
Write Operation
MOD
IAR
0
D3
IA3
0
D2
IA2
20
C1
D1
IA1
Read Operation
STA
IAR
C0
D0
IA0
Bit 0
Control Byte
Data Byte
Address Byte
PEB 2045
PEF 2045