pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 15

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

PEB 2045
PEF 2045
As can be seen there the beginning of a input time-slot is defined such, that the input lines have
settled to a stable value, when the datum is actually sampled.
4096- and 8192-kbit/s data is sampled in the middle of the bit period at the falling edge of the
respective data clock. 2048-kbit/s data is sampled after 3/4 of the according bit period, i.e. with the
th
nd
rising edge of the 4
8192-kHz clock cycle or the falling edge of the 2
4096-kHz clock cycle of the
considered bit period.
In the primary access configuration a different timing scheme may apply to the odd input lines. They
are affected by the content of the clock shift register (CSR), which can be programmed via the P
interface (see section Indirect Register Access).
The clock shift register holds the information, how the frame structure is shifted in the primary
access configuration. Its content defaults to 00
after power up and is also set to this value,
H
whenever the standard configuration is selected.
The four most significant bits of the clock shift register are of interest for the input lines. They only
affect the odd input lines (see section Clock Shift Register Access): The frame structure can be
advanced by the number of bit periods programmed to the RS2, RS1 and RS0 bits of the CSR. For
example, programming the CSR with (1100XXXX) a new frame starts 6-bit periods before the rising
edge of the SP pulse.
Selecting RRE to logical 1 the frame is delayed by half a bit period (see figure 9). The data is then
sampled in the middle of the respective bit period for all data rates.
The last line of figure 9 shows the sampling instants for the CSR entry (1001XXXX). Then the input
frame is advanced by 4-bit periods and delayed by a half resulting in an 3 1/2-clock period
advancement of the input frame. For further examples refer to figure 21.
Thus the frame structure may be selected to begin at any 1/2-bit period value between a resulting
advancement of 7-bit periods and a resulting delay of 1/2 a bit period.
Setting CSR = 0X
the same timing conditions apply to even and odd inputs. Then all system
H
interface inputs are processed in the same way they are in the standard configuration.
Speech Memory
The prepared input data is written into the speech memory SM. It has a capacity of 512 bytes to
store one frame of all active input lines. The destination SM addresses are supplied by the input
counter, which resides in the timing control block. They ensure that a certain input channel is always
written to the same physical speech memory location. The input counter is synchronized with the
rising edge of the SP signal.
The 9-bit addresses to read the speech memory are supplied by the connection memory. These are
programmable and need not follow any recognizable sequence.
Write and read accesses of the SM occur alternately.
Connection Memory
The connection memory (CM) is a RAM organized as 256
10 bits. It contains the 9-bit speech
memory address and a validity bit for the 256 possible output channels. While the speech memory
address points to a location in the SM, the validity bit is processed in the timing control block: If the
TE bit in the mode register (see paragraph 4.1) is set to logical 0, the validity bit is directly
Semiconductor Group
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