pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 16

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

forwarded to the output buffer as the tristate control signal. Otherwise (if TE = high), an all-zero
speech memory address causes the output for the associated channel to be tristate. In this case the
all-zero speech memory address (time-slot 0 on output line 0) cannot be used for switching
purposes.
Figure 10
The Influence of the Connection Memory on the Output Validity
The CM is written via the P interface using the indirect register access scheme (see section
Indirect Register Access). It is read using addresses supplied by the output counter which resides
in the timing control block. The output counter generates addresses that form an enumerative
sequence. Thus the connection memory is read cyclically and establishes the correct time-slot
sequence of the outputs.
The output counter is synchronized with the falling and rising edge of the SP signal in standard and
primary access configurations, respectively.
The connection memory addresses and data encode the number of the output and input channels,
respectively. For a detailed description of the code please refer to section Indirect Register
Access and Connection Memory Access.
Semiconductor Group
Bit7
Output Time-Slot + Line #
Address
Bit0
CM
= 1?
Bit9
Va Input Time-Slot + Line #
YES
TE = 0
16
Tristate Enable Bit
Content
Bit 8-0
= O ?
Mode Register
H
YES
TE = 1
Connection Tristated
Otherwise Enabled
ITD03658
PEB 2045
PEF 2045