pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 3

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

1.1
Pin No.
P-LCC
1
3
4
7
9
11
13
14
15
16
17
18
19
5
8
10
12
20
21
22
23
24
Semiconductor Group
Pin Definitions and Functions
Pin No.
P-DIP
1
2
3
5
7
9
11
12
13
14
15
16
17
4
6
8
10
18
19
20
21
22
Symbol
V
SP
IN1
IN5
IN9
IN13
IN14
IN15
IN10
IN11
IN6
IN7
IN2
IN0/TSC0
IN4/TSC1
IN8/TSC2
IN12/TSC3
IN3/DCL
A0
CS
V
RD
SS
DD
Input (I)
Output (O)
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I
I
I
I
3
Function
Ground (OV)
Synchronization Pulse: The PEx 2045 is
synchronized relative to the PCM system via
this line.
PCM-Input Ports: Serial data is received at
these lines at standard TTL levels.
PCM-Input Port / Tristate Control: In standard
configuration these pins are used as input lines,
in primary access configuration they supply
control signals for external devices.
PCM-Input Port / Data Clock: In standard
configuration IN3 is the PCM input line 3, in
primary access configuration it provides a
2048-kHz data clock for the synchronous
interface.
Address 0: When high, the indirect register
access mechanism is enabled. If A0 is logical 0
the mode and status registers can be written to
and read respectively.
Chip Select: A low level selects the PEx 2045
for a register access operation.
Supply voltage: 5 V 5 %.
Read: This signal indicates a read operation
and is internally sampled only if CS is active.
The MTSC puts data from the selected internal
register on the data bus with the falling edge of
RD. RD is active low.
PEB 2045
PEF 2045